New low power delay element in self resetting logic with modified Gated Diffusion Input technique

Ramadass, Uma; Dhavachelvan, P.

doi:10.1109/smelec.2012.6417197

Cited by 6 publications

(2 citation statements)

References 16 publications

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“…The number of attributes defined in the delay and power model incorporates minimum variables without sacrificing precision. [24][25][26][27][28][29] (logic family) that resembles a CMOS inverter design, and it consists of a series of connected pMOS and nMOS with shorted gate input. In GDI, at the drain terminal of pMOS, the upper region is tied to the P-diffusion, while the lower region of nMOS, at the source terminal, is connected to the Ndiffusion input instead of the power rail and ground.…”

Section: -2-aim Goal and Objectivesmentioning

confidence: 99%

A Unified Power-Delay Model for GDI Library Cell Created Using New Mux Based Signal Connectivity Algorithm

Ponnian¹,

Pari²,

Ramadass³

et al. 2023

Emerg Sci J

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The challenges of innovative IC technology typically come with various new design constraints in terms of circuit implementation, behaviour, scaling, and an accurate power-delay model to evaluate the circuit's performance. The circuit realization technique using GDI is gaining popularity because of its power and transistor utilization factors. Considering the core advantage of the GDI technique, this research presents the creation of new GDI library cells implemented using the MUX-based algorithm and its delay-power model. This research defines two goals; the former goal depicts the proposal of GDI library cells with full swing using a MUX-based signal connectivity model, and the later presents the mathematical delay-power model for the proposed GDI library cells. The number of attributes defined in the delay and power model incorporates minimum variables without sacrificing precision. It calculates the delay for simple RC networks and combinational circuits with multiple paths. The power model is given using the node activity factor and the power factor related to the internal node capacitances, wiring, and gate capacitances of the driving and receiving GDI nodes. The experimental results of this study, which conform to the specifications of the sub-micron library supported for the SilTerra 130 nm 6-metal layer fabricated for the CMOS n-well process, demonstrate that the proposed GDI library is indeed superior in terms of delay-transistor and power utilisation to PTL and CMOS technology. The simulation results reveal that there is 55 to 65 % improvement in terms of power and delay factor with the existing CMOS and PTL logic. The proposed delay model demonstrates that GDI cells require less logical effort than CMOS technology. The proposed power model shows that the node activity factor of the proposed GDI cells lies between 0.1 and 0.2, while in CMOS, it is between 0.1 and 0.3. Doi: 10.28991/ESJ-2023-07-04-022 Full Text: PDF

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Section: -2-aim Goal and Objectivesmentioning

confidence: 99%

A Unified Power-Delay Model for GDI Library Cell Created Using New Mux Based Signal Connectivity Algorithm

Ponnian¹,

Pari²,

Ramadass³

et al. 2023

Emerg Sci J

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“…Due to reduction in short circuit current this technology used in the repeaters and synthesizers implementation. The DC transient analysis was also better as compared to the GDI and CMOS[31].Krishnendu Dhar et al designed FULL ADDER using MGDI AND MVT technique. Mixed threshold technique with MGDI used to improve the performance of adder.…”

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confidence: 99%

Gate Diffusion Input Technique for Power Efficient Circuits and Its Applications

2019

ijrte

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In present scenario world become completely digital. In digital devices the speed and life of the battery is the biggest issue .To resolve these problems there are my techniques for design the devices. A low power design technique is Gate Diffusion input (GDI). This review has the study of GDI technique which is most recent research in low power designing field. In this study many paper were reviewed. The review has structure of THE GDI cell, modeling and application. This review also presented the comparison of GDI technique with other technique of designing. The purpose of the study to find out most recent research in field of GDI. From this study we find out this technique mostly used for digital circuits. This review provides the current state of research and future scopes in this field.

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New low power adders in Self Resetting Logic with Gate Diffusion Input Technique

Uma

Ponnian

Dhavachelvan

2017

Journal of King Saud University - Engineering Sciences

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New low power delay element in self resetting logic with modified Gated Diffusion Input technique

Cited by 6 publications

References 16 publications

A Unified Power-Delay Model for GDI Library Cell Created Using New Mux Based Signal Connectivity Algorithm

A Unified Power-Delay Model for GDI Library Cell Created Using New Mux Based Signal Connectivity Algorithm

Gate Diffusion Input Technique for Power Efficient Circuits and Its Applications

New low power adders in Self Resetting Logic with Gate Diffusion Input Technique

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