Non-Blocking Testing for Network-on-Chip

Huang, Letian; Wang, Junshi; Ebrahimi, Masoumeh; Daneshtalab, Masoud; Zhang, Xiaofan; Li, Guangjun; Jantsch, Axel

doi:10.1109/tc.2015.2489216

Cited by 18 publications

(3 citation statements)

References 27 publications

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“…For the detached core, they also provide alternative connections during the test time. Huang et al [39] also presented another non-blocking testing for Networkon-Chips. A testing for NoC fabrics is presented in [40], which can be applied for 3D-NoCs, uses dedicated test data and structure.…”

Section: A Test Schedulingmentioning

confidence: 99%

A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

et al. 2020

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Through-Silicon-Via (TSV) based 3D Integrated Circuits (3D-IC) are one of the most advanced architectures by providing low power consumption, shorter wire length and smaller footprint. However, 3D-ICs confront lifetime reliability due to high operating temperature and interconnect reliability, especially the Through-Silicon-Via (TSV), which can significantly affect the accuracy of the applications. In this paper, we present an online method that supports the detection and correction of lifetime TSV failures, named IaSiG. By reusing the conventional recovery method and analyzing the output syndromes, IaSiG can determine and correct the defective TSVs. Results show that within a group, R redundant TSVs can fully localize and correct R defects and support the detection of R + 1 defects. Moreover, by using G groups, it can localize up to G × R and detect up to G × (R + 1) defects. An implementation of IaSiG for 32-bit data in eight groups and two redundancies has a worst-case execution time (WCET) of 5,152 cycles while supporting at most 16 defective TSVs (50% localization). By integrating IaSiG onto a 3D Network-on-Chip, we also perform a grid-search based empirical method to insert suitable numbers of redundancies into TSV groups. The empirical method takes the operating temperature as the factor of accelerated fault due to the fact that temperature is one of the major issues of 3D-ICs. The results show that the proposed method can reduce the number of redundancies from the uniform method while still maintaining the required Mean Time to Failure.

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Section: A Test Schedulingmentioning

confidence: 99%

A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

et al. 2020

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“…A gridlock free and exceptionally versatile directing calculation is a proposed to help reconfigurations for testing. Moreover, testing grouping is characterized to enable testing various switches to abstain from dropping of bundles.Methodology is proposed to control the conduct of the influenced parcels amid the change of a switch from ordinary to the testing mode and the other way around .By This methodology neither interferes with the execution of utilizations nor significantly affects the execution time [9].…”

Section: International Journal Of Innovative Technology and Exploringmentioning

confidence: 99%

Development of an Efficient Router Based on Network on Chip Network

N*,

K.R

2020

IJITEE

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A reconfigurable VLSI architecture for router is the main solution for communication interface quality of service go flexibility of network, cost of chip .The proposed architecture dynamically configure itself with respect to hardware modules such as packet based switch, router and data packet size by changing the conditions of communication and it's requirement at run time .In network on chip were using extended XY algorithm to improve performance of communication. The proposed design work avoids the dead lock and data loss in the path with the help of this design we can achieve high Data through put and low latency .in this paper we are receiving the previous method and approaches of dynamic reconfigurable router in network on chip

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“…If channels of all complete pairs are numbered from 1 to 2K, and traced in an ascending order (or descending order), the formed U-turns do not lead to deadlock. Note to Theorem2: Enabling U-turns is essentially important in fault-tolerant designs or where rerouting brings an advantage (see [22]). In addition, topologies with wrap-around channels can utilize U-turns.…”

Section: Theoremsmentioning

confidence: 99%

EbDa

Ebrahimi

Daneshtalab

2017

Proceedings of the 44th Annual International Symposium on Computer Architecture

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Freedom from deadlock is one of the most important issues when designing routing algorithms in on-chip/off-chip networks. Many works have been developed upon Dally's theory proving that a network is deadlock-free if there is no cyclic dependency on the channel dependency graph. However, finding such acyclic graph has been very challenging, which limits Dally's theory to networks with a low number of channels. In this paper, we introduce three theorems that directly lead to routing algorithms with an acyclic channel dependency graph. We also propose the partitioning methodology, enabling a design to reach the maximum adaptiveness for the n-dimensional mesh and k-ary n-cube topologies with any given number of channels. In addition, deadlock-free routing algorithms can be derived ranging from maximally fully adaptive routing down to deterministic routing. The proposed theorems can drastically remove the difficulties of designing deadlock-free routing algorithms. CCS CONCEPTS• Computer systems organization → Interconnection architectures;

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Non-Blocking Testing for Network-on-Chip

Cited by 18 publications

References 27 publications

A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

Development of an Efficient Router Based on Network on Chip Network

EbDa

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