Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology

Abstract

This paper presents a novel clocking scheme for the Favrat charge pump topology. The proposed clock scheme achieves an 8 % higher maximum power output and a 12 % higher maximum output voltage than the prior-art clock scheme. The novel clock scheme is part of the development of a very high voltage charge pump for MEMS applications. In this work a 46stage charge pump based on the Favrat charge pump topology has been fabricated in a 180-nm SOI process with a > 200 V breakdown voltage. With an input voltage of 5 V the fabricated charge pump reach an output voltage of 185 V when driven by the proposed clock scheme and loaded with a 2 nA load, the prior-art clock scheme can only reach an output voltage of 165 V with a 2 nA load.

A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process

“…By adding a single capacitor and two transistors to the Pelliconi topology, the Favrat [19] topology, as illustrated in [20], Fig. 1, can be realised.…”

“…The charge pump is clocked using a crossing clock scheme, instead of the non-overlapping clock scheme used in literature [15], [19], as the crossing clocks, Clk A and Clk B in Figs. 1-3, reduce the reverse currents and thereby achieve a higher voltage gain [20].…”

“…To reduce ripple on the output of the charge pump, an output filter was implemented as depicted in Fig. 4 as illustrated in [20], Fig. 2.…”

“…If the size of the ESD protection and output filter is not considered, the implementations in [9], [14], [20] are of similar area as the charge pump cores of this work, but only achieve step-up ratios of respectively 3.2, 19, and 13.1, while also having a significantly higher input power. In [9], where no input power or efficiency specification was available, it must be assumed that the input power is at least the same as the output power, which is up to 44 times higher than the input power in this work.…”