Novel energy-efficient scalable soft-output SSFE MIMO detector architectures

Fasthuber, Robert; Li, Min; Novo, David; Raghavan, Praveen; Perre, Liesbet Van der; Catthoor, Francky

doi:10.1109/icsamos.2009.5289228

Cited by 20 publications

(8 citation statements)

References 11 publications

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“…Table 6 shows the comparison results of our design and the existing 2x2 MIMO symbol detectors [16,[22][23][24][25]. For the fair comparison, four normalized metrics are considered such as normalized area (NA), normalized power (NP), normalized hardware efficiency (NHE) and normalized power efficiency (NPE): ML and MML [14] SOSD w/ MRTS [11] MFCSO [16] LORD [22] SSFE [23] K-Best(K=10) [24] SQRDML [25] Proposed, floating-pts Proposed, fixed-pts …”

Section: Implementation and Verification Resultsmentioning

confidence: 99%

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Low-Complexity and Low-Power MIMO Symbol Detector for Mobile Devices with Two TX/RX Antennas

Jang¹,

Lee²,

Jung

2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a low-complexity and lowpower soft output multiple input multiple output (MIMO) symbol detector is proposed for mobile devices with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in single hardware and shows the optimal maximum likelihood (ML) performance. By applying a multistage pipeline structure and using a complex multiplier based on the polar-coordinate, the complexity of the proposed architecture is dramatically decreased. Also, by applying a clockgating scheme to the internal modules for MIMO modes, the power consumption is also reduced. The proposed symbol detector was designed using a hardware description language (HDL) and implemented using a 65nm CMOS standard cell library. With the proposed architecture, the proposed MIMO detector takes up an area of approximately 0.31mm 2 with 183K equivalent gates and achieves a 150Mbps throughput. Also, the power estimation results show that the proposed MIMO detector can reduce the power consumption by a maximum of 85% for the various test cases.

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Section: Implementation and Verification Resultsmentioning

confidence: 99%

“…Also, SSFE [23] shows the near ML performance, however, the throughput and NPE are lower than those of the proposed detector. Even though the NHE of the detector [24] is higher than the proposed detector, the results in [24] do not include the channel pre-processor. Also, it cannot support ML performance and has lower NPE.…”

Section: Powermentioning

confidence: 99%

Low-Complexity and Low-Power MIMO Symbol Detector for Mobile Devices with Two TX/RX Antennas

Jang¹,

Lee²,

Jung

2015

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…The control unit, which generates control signals for the datapath and the output, is implemented In general, it can be pessimistically assumed that the throughput scales linearly with area and power. More information about the scalability of this architecture can be found in [9].…”

Section: Architecturementioning

confidence: 99%

“…Because the ASIC is based on the optimized SSFE and LLR algorithm, it is more efficient than other state-of-theart ASICs. A comparison is provided in [9]. Table 5 summarizes the maximal achievable throughput, the area consumption and the power consumption of the MIMO detector implementations considered in this work.…”

Section: Area and Power Estimationsmentioning

confidence: 99%

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Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors

Fasthuber

Novo

et al. 2010

J Sign Process Syst

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Emerging Software Defined Radio (SDR) baseband platforms are based on multiple processors with massive parallelism. Although the computational power of these platforms would theoretically enable SDR solutions with advanced wireless signal processing, existing work implements still rather basic algorithms. For instance, current Multiple-Input Multiple-Output (MIMO) detector implementations are typically based on simple linear hard-output and not on advanced near-Maximum Likelihood (ML) soft-output detection. However, only the latter enables to exploit the full potential of MIMO technology. In this work, we explore the feasibility of advanced soft-output near-ML MIMO detectors on massive parallel processors. Although such detectors are considered to be very challenging due to their high computational complexity, we combine architecture-friendly algorithm design, application

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An Improved K-Best MIMO Detection Algorithm for Parallel Programmable Baseband Architecture

Tan

Zhao

Zhou

et al. 2013

Lecture Notes in Electrical Engineering

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Novel energy-efficient scalable soft-output SSFE MIMO detector architectures

Cited by 20 publications

References 11 publications

Low-Complexity and Low-Power MIMO Symbol Detector for Mobile Devices with Two TX/RX Antennas

Low-Complexity and Low-Power MIMO Symbol Detector for Mobile Devices with Two TX/RX Antennas

Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors

An Improved K-Best MIMO Detection Algorithm for Parallel Programmable Baseband Architecture

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