Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System

Dalmia, Preyesh; Vikas, .; Parashar, Abhinav; Tomar, Akshi; Pandey, Neeta

doi:10.1109/vlsid.2018.78

Cited by 7 publications

(1 citation statement)

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“…Due to expanding of computer and signal processing utilization, the attention of excessive speed processing has been expanding gigantically. Design of regular and simple structure that multiplier should have increase speed, reduce area and reduce power [10].…”

Section: Introductionmentioning

confidence: 99%

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

Gavaskar¹,

Malathi²,

Ravivarma³

et al. 2021

Wireless Pers Commun

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The Multiply Accumulate (MAC) unit constructed using antiquated Vedic mathematical practice and the e ciency of the vertical and transversely of Vedic approach for multiplication, which gives a distinction in genuine cycle of Multiplier itself. Vedic-Mathematics is depend on 16-Sutras, in that Urdhva-Triyakbhyam (UT) more productive one. It literally means vertical and cross wise operations. It eliminates unwanted multiplication and allows the parallel creation of partial products and addition steps. The adders are utilized to append the partial-product generated in the Vedic mathematics methodology to drops the combinational lag. MAC is an essential unit in the digital signal processors, to show the characters like speed, power as well as area. Hence, ner multiplier plans are to increase the order of the system. The Modi ed sum product algorithm based Vedic multiplier is one such promising solution. It has a rapid multiplication process and reaches a less calculation complexity above its traditional multiplier. Array multiplier, Baugh-Wooley multiplier, Wallace-tree multiplier and Vedic multiplier were created in the existing work. In proposed work Vedic multiplier, using modi ed sum product algorithm was designed. The structure design coded in verilog and parameter analysis was done in Xilinx. The parameters like delay as well as power were compare between existing and proposed. When comparing with different multiplier with our proposed work delay get reduced. Comparing with existing multiplier the proposed 4x4 Vedic multiplier have 49.12% reduction in delay. Comparing with existing multiplier the proposed Vedic 4x4 multiplier have 42.51% reduction in power.

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Section: Introductionmentioning

confidence: 99%