Novel Low‐Latency T‐Latch with Minimum Number of Cells in QCA Technology

Abstract

As an alternative to nanoelectronic devices, the quantum‐dot cellular automata (QCA) offer new opportunities to design high‐level algorithms and architectures. Using parallel processing, high speed, and low energy consumption, this emerging technology is very suitable and efficient for operational needs that require a large amount of computing and are often time consuming. In this paper, a new and optimal T‐latch design is introduced. The proposed latch structure has less occupied area and energy consumption than the existing implementation methods. In the proposed T‐latch the cell, area and energy consumption are reduced by 9.52%, 6.45%, and 19.67% compared to the best previous designs, respectively. Also, in this article, the T‐latch with reset and T‐latch with set/reset terminals are designed. Then, using the proposed T‐latch, various other latches are designed to ensure the correct operation of the designed T‐latch. Finally, to show that the proposed latch works properly in more complex circuits, they are used in the design of 1‐bit, 4‐bit, and n‐bit counters and the results of the simulations show the proper operation of the circuit. The proposed methods are simulated using the QCADesigner software and compared with other designs in terms of cell number, area, and energy consumption.