Novel Memristor Emulators using Fully Balanced VDBA and Grounded Capacitor

Yadav, Nisha; Kumar, Shireesh; Pandey, Rishikesh

doi:10.1007/s40998-020-00357-x

Cited by 29 publications

(11 citation statements)

References 59 publications

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“…By connecting sub-circuits based on the block diagram in Figure 15, the proposed floating series inductance-resistance simulator is achieved, as shown in Figure 16. For gm1 = gm2 = gm, the input impedance between the first and second port of Figure 16 is given by Equation (8) shows that the circuit presented in Figure 16 simulates the impedance of the floating series connection inductor-resistor, where its equivalent inductance value is the same as that given by ( 4) and the series resistance is given by…”

Section: The Proposed Floating Series Inductance-resistance Simulatormentioning

confidence: 99%

“…With this structure, the VDBA has a low output impedance and high input impedance, which is useful in circuit design, since active blocks can be cascaded in voltage-mode circuits, without the requirement of additional voltage buffers [5,6]. VDBA-based circuits can be found in the open literature [7][8][9][10][11][12][13][14][15][16][17]. However, in some applications, the unity gain voltage differencing circuit is required, which cannot be directly realized with VDBAs.…”

Section: Introductionmentioning

confidence: 99%

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Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs

et al. 2021

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This paper presents inductance simulators using the voltage differencing differential input buffered amplifier (VD-DIBA) as an active building block. Three types of inductance simulators, including floating lossless inductance, series inductance-resistance, and parallel inductance-resistance simulators, are proposed, in addition to their application to the 4th order elliptic lowpass ladder filter. The simple design procedures of these inductance simulators using a circuit block diagram are also given. The proposed inductance simulators employ two VD-DIBAs and two passive elements. The complementary metal oxide semiconductor (CMOS) VD-DIBA used in this design utilizes the multiple-input metal oxide semiconductor (MOS) transistor technique in order to achieve a compact and simple structure with a minimum count of transistors. Thanks to this technique, the VD-DIBA offers high performances compared to the other CMOS structures presented in the literature. The CMOS VD-DIBAs and their applications are designed and simulated in the Cadence environment using a 0.18 µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). Using a supply voltage of ±0.9 V, the linear operation of VD-DIBA is obtained over a differential input range of −0.5 V to 0.5 V. The lowpass (LP) ladder filter realized with the proposed inductance simulators shows a dynamic range (DR) of 80 dB for a total harmonic distortion (THD) of 2% at 1 kHz and a 1.8 V peak-to-peak output. In addition, the experimental results of the floating inductance simulators and their applications are obtained by using VD-DIBA constructed from the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental ones, confirming the advantages of the inductance simulators and their application.

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Section: The Proposed Floating Series Inductance-resistance Simulatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs

et al. 2021

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“…There are several challenges to implementing the SNN inspired by biological neural sensors systems based on memristor as a synapse, such as reliability, compatibility with CMOS technology, the fabrication complexity of memristor systems, the lifetime of memristor devices, the finite number of resistance levels, and resistance level stability (Krestinskaya et al, 2019;Zhang et al, 2020). Therefore, one more class of researchers have focused on memristor emulators to implement memristor SNN architectures on contemporary chips (Babacan et al, 2017;Cao and Wang, 2021;Kanyal et al, 2018;Prasad et al, 2021;Sánchez-López et al, 2014;Yadav et al, 2021;König, 2020, 2021b). Compared to the CMOS-based memristor, the material-based type offers more advantages beyond Moore technology to support a much more compact design and less power consumption.…”

Section: Introductionmentioning

confidence: 99%

“…Likewise, Sánchez-López et al (2014) proposed a memristor emulator with a single multiplier and four second generation current conveyors (CCII). Yadav et al (2021) also proposed a memristor circuit utilizing a fully balanced voltage differencing buffered amplifier (FB-VDBA) and capacitor. They emulated the LTP function by utilizing external memory, digital-to-analog converter (DAC), and a big external capacitor.…”

Section: Introductionmentioning

confidence: 99%

Design of a CMOS memristor emulator-based, self-adaptive spiking analog-to-digital data conversion as the lowest level of a self-x hierarchy

Abd

König

2022

J. Sens. Sens. Syst.

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Abstract. The number of sensors used in modern devices is rapidly increasing, and the interaction with sensors demands analog-to-digital data conversion (ADC). A conventional ADC in leading-edge technologies faces many issues due to signal swings, manufacturing deviations, noise, etc. Designers of ADCs are moving to the time domain and digital designs techniques to deal with these issues. This work pursues a novel self-adaptive spiking neural ADC (SN-ADC) design with promising features, e.g., technology scaling issues, low-voltage operation, low power, and noise-robust conditioning. The SN-ADC uses spike time to carry the information. Therefore, it can be effectively translated to aggressive new technologies to implement reliable advanced sensory electronic systems. The SN-ADC supports self-x (self-calibration, self-optimization, and self-healing) and machine learning required for the internet of things (IoT) and Industry 4.0. We have designed the main part of SN-ADC, which is an adaptive spike-to-digital converter (ASDC). The ASDC is based on a self-adaptive complementary metal–oxide–semiconductor (CMOS) memristor. It mimics the functionality of biological synapses, long-term plasticity, and short-term plasticity. The key advantage of our design is the entirely local unsupervised adaptation scheme. The adaptation scheme consists of two hierarchical layers; the first layer is self-adapted, and the second layer is manually treated in this work. In our previous work, the adaptation process is based on 96 variables. Therefore, it requires considerable adaptation time to correct the synapses' weight. This paper proposes a novel self-adaptive scheme to reduce the number of variables to only four and has better adaptation capability with less delay time than our previous implementation. The maximum adaptation times of our previous work and this work are 15 h and 27 min vs. 1 min and 47.3 s. The current winner-take-all (WTA) circuits have issues, a high-cost design, and no identifying the close spikes. Therefore, a novel WTA circuit with memory is proposed. It used 352 transistors for 16 inputs and can process spikes with a minimum time difference of 3 ns. The ASDC has been tested under static and dynamic variations. The nominal values of the SN-ADC parameters' number of missing codes (NOMCs), integral non-linearity (INL), and differential non-linearity (DNL) are no missing code, 0.4 and 0.22 LSB, respectively, where LSB stands for the least significant bit. However, these values are degraded due to the dynamic and static deviation with maximum simulated change equal to 0.88 and 4 LSB and 6 codes for DNL, INL, and NOMC, respectively. The adaptation resets the SN-ADC parameters to the nominal values. The proposed ASDC is designed using X-FAB 0.35 µm CMOS technology and Cadence tools.

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“…Voltage-tunable fully balanced voltage differencing buffered amplifier (FB-VDBA) based memristor emulator was presented by Yadav et.al. in 2019 [29]. Yesil et.al, had proposed an electronically tunable memristor using only one voltage differencing current conveyor (VDCC) [30].…”

Section: Introductionmentioning

confidence: 99%

Charged Controlled Mem-Element Emulator and Its Application in a Chaotic System

et al. 2020

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This paper proposes a charged controlled emulator model for memristor and memcapacitor using second-generation Current Conveyor (CCIIs) and Analog Multiplier (AM). The grounded and floating memelement circuits have been designed using two CCIIs and one multiplier in addition to some passive components. The grounded type of design requires three resistors and three capacitors while floating design necessitates only two resistors and two capacitors. With the help of a switch, the proposed design can be easily switched into a memristor or memcapacitor. The proposed emulator model has been theoretically analyzed and simulated in PSpice to substantiate the effectiveness and accuracy. The practicability of the circuit has been established using commercially available ICs AD844AN and AD633JN. Non-linear characteristics of the proposed memristor emulator have been used to design a chaotic system.

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Novel Memristor Emulators using Fully Balanced VDBA and Grounded Capacitor

Cited by 29 publications

References 59 publications

Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs

Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs

Design of a CMOS memristor emulator-based, self-adaptive spiking analog-to-digital data conversion as the lowest level of a self-x hierarchy

Charged Controlled Mem-Element Emulator and Its Application in a Chaotic System

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