On-chip impulse response generation for analog and mixed-signal testing

Singh, Amar; Patel, Chintan; Plusquellic, Jim

doi:10.1109/test.2004.1386960

Cited by 14 publications

(5 citation statements)

References 9 publications

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“…Several testing techniques for analogue circuits are attempted. Some testing approaches aim to test analogue circuits based on approximated impulse and step test signals [14][15][16][17][18][19][20]. The limitation of these approaches is the requirements generation of the ideal impulse.…”

Section: Fig 1 Classification Of Analogue Circuit Faultsmentioning

confidence: 99%

New Digital Testing of Analogue Circuits

El-Mahlawy

Mahmoud

Gadallah

et al. 2015

International Conference on Aerospace Sciences and Aviation Tec

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This paper presents a new parametric fault detection approach for analogue circuits based on the digital signature analysis. This approach has two main parts, an analogue test pattern generator (ATPG), and an analogue test response compactor (ATRC). The proper ATPG is designed to sweep the applying sinusoidal frequencies to match the frequency domain of the analogue circuit under test (ACUT). The output test response of the ACUT is acquired via the analogue-to-digital converter (ADC). The ATRC accumulates digital samples of the output response from the ADC to generate a digital signature that can characterize the situation of the ACUT. The signature comparison is achieved based on signature boundaries and the worst-case analysis. In addition, the signature curve for each component variations in the ACUT is presented. It combines effective parameters of the transfer function of the ACUT with respect to the component variations. These parameters are the band-width and the passband transmission. In this paper, the hardware implementation is achieved using the field programmable gate array (FPGA) technology as the digital part and the analogue part that includes the data conversion. The digital test controller is designed to enable the proper control and synchronization of the analogue test cycle for stable digital signature generation. The presented testing approach is applied to the ACUT in the range of biomedical applications to validate it. Based on the presented hardware implementation, the signature curve for each component of the ACUT is derived for the ACUT judgment.

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Section: Fig 1 Classification Of Analogue Circuit Faultsmentioning

confidence: 99%

New Digital Testing of Analogue Circuits

El-Mahlawy

Mahmoud

Gadallah

et al. 2015

International Conference on Aerospace Sciences and Aviation Tec

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“…Recently, the simple pulse generation circuit based on a differentiator has been proposed in [14] for alleviating the complexity in on-chip pattern generations and cross-correlation operations. However, fault detection is performed statistically by means of linear regression analysis that necessitates specific algorithms and external software.…”

Section: Existing On-chip Testing Tech-niques and System Implementa-t...mentioning

confidence: 99%

A Low-Cost High-Speed Pulse Response Based Built-In Self Test For Analog Integrated Circuits

San-Um

Tachibana

2009

ECTI-EEC

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This paper presents a pulse response-based builtin self test technique and implementation for the testing of analog integrated circuits in mixed-signal systems. This BIST technique employs two narrow width pulses as input stimuli, and monitors two voltage samples on pulse response waveform for fault detection through allowable tolerances. The BIST system implementation realizes a programmable delay line for generating pulse stimuli, and a sample-and-hold circuit with comparators for fault detection process. Demonstrations of the testing for a Sallen-Keylow-pass ¯lter using 0.18-?m CMOS technology yields relatively high fault coverage. The fault coverage of catastrophic faults is 100%, and the fault coverage of capacitor and resistor variations are 93.75% and 87.5%, respectively. The proposed BIST technique uses low testing time within two short pulse response waveforms, and o®ers low implementation cost since onchip sinusoidal stimuli, test algorithms, and external digital processing unit are not necessary.

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“…Several testing techniques for analogue circuits are attempted. Some testing approaches aim to test analogue circuits based on approximated impulse and step test signals [11][12][13][14][15][16][17]. The limitation of these approaches is the requirements generation of the ideal impulse.…”

Section: Introductionmentioning

confidence: 99%

Parametric Fault Detection of Analogue Circuits

Anis¹,

El-Mahlawy²,

Gadallah³

et al. 2014

IJCA

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This paper presents a new testing approach for analogue circuits based on the digital signature analysis. In this paper, the efficient parametric fault detection approach for analogue circuits using the simulation environment is presented. This approach has three main parts, an analogue test pattern generator (ATPG), an analogue test response compactor (ATRC), and an analogue circuit under test (ACUT) model, build in the PSpice circuit simulator. The proper ATPG is designed to sweep the applying sinusoidal frequencies to match the frequency domain of the ACUT. The output test response of the ACUT is acquired via the analogue-to-digital converter (ADC). The ATRC accumulates digital samples of the output response from the ADC to generate a digital signature that can characterize the situation of the ACUT. The signature comparison is achieved based on signature boundaries based on the worst-case analysis. In addition, the signature curve for each component variations of the ACUT is presented to be illustrated as image of some parameters affected in the transfer function of the ACUT. It combines effective parameters of the transfer function of the ACUT with respect to the component variations. These parameters are the band-with and the passband transmission. Using the signature curve, a parametric fault of each component of the ACUT can be detected under the sweep sinusoidal frequency of the ATPG. The presented testing approach is applied to the analogue benchmark circuit to validate the presented testing approach.

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On-chip impulse response generation for analog and mixed-signal testing

Cited by 14 publications

References 9 publications

New Digital Testing of Analogue Circuits

New Digital Testing of Analogue Circuits

A Low-Cost High-Speed Pulse Response Based Built-In Self Test For Analog Integrated Circuits

Parametric Fault Detection of Analogue Circuits

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