On codes with summation of data bits in concurrent error detection systems

Abstract

We consider a complete set of codes with unit bits summation used to organize combinational logic in logical devices. We propose new modified codes and establish their data bits errors detection properties. We also give a classification of codes.

The Synthesis of Self-Checking Combinational Devices on the Basis of Codes with the Effective Symmetrical Error Detection

“…Например, к такому коду относится описанный в [49] Abstract. The methods of fault-tolerant coding are often used in the designing of reliable and safety components of automatic control systems: both in the data transmission between system nodes, and at the level of hardware and software architecture.…”