On performance scaling and speed of junctionless transistors

Koukab, Adil; Jazaeri, Farzan; Sallèse, Jean-Michel

doi:10.1016/j.sse.2012.08.001

Cited by 28 publications

(6 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These different techniques are majorly implemented on the structure of abundant devices. The study on speed and performance of the junctionless transistor is carried out by the authors in [43]. By implementing all such types of distinct approaches, the researchers can easily understand the physics of the junctionless transistor to the depth and get familiar with the characteristics of drain current on varying different design parameters.…”

Section: Image Sensorsmentioning

confidence: 99%

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

View full text Add to dashboard Cite

The Short Channel Effects (SCE) are becoming more prominent in Complementary Metal Oxide Semiconductor (CMOS) circuits with an introduction of nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The short channel effects (SCE’s) and fabrication challenges have provoked the researchers to think for some other technologies to enhance the market of semiconductor devices. To overcome these SCE’s, various methodologies such as multi-gate structures, material engineering, gate engineering, dielectric pockets, strain technology, high K dielectric material, heterostructures, source and drain extensions etc. have been implemented. However, at very short channel lengths, the sharp edges of doping are difficult to obtain and thus SCE’s have become so difficult to control even after the implementations of different methodologies. Therefore, a new type of technology has been introduced to overcome such pitfalls e.g. transistors without junctions. Junctionless field effect transistor (JLFET) is one of the technologies which has overcome various SCE’s. Although the research on various issues has been addressed by different authors but still there is an impediment in the commercialization of the same device. The different technology boosters have been incorporated into junctionless based devices to escalate the performance. The technology boosting aspect of junctionless FET has been reviewed in this paper which has not been considered yet. In this paper distinct technology boosters and numerous effects on junctionless devices have been studied and presented. The performance of the junctionless FET devices are studied on incorporating the different semiconductor materials, effect of strain, use of high k dielectric, use of dielectric pockets, effect of gate misalignment, use of heterostructures, silicon on nothing (SON), vertically stacked nanowires, newly proposed rectangular core-shell based junctionless FET’s and roles of various physical parameters such as temperature, nanowire widths and effect of scattering mechanism on the performance of JLFET have been addressed.

show abstract

Section: Image Sensorsmentioning

confidence: 99%

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

View full text Add to dashboard Cite

show abstract

“…So, to deal with this issue, another device, junctionless transistor (JLT) 8–11 was introduced, in which absence of junctions provides improved electrical properties, lower leakage current and easy fabrication. But, JLT also possesses decaying carrier's mobility leading to decreased drain current and transconductance 12–14 . To eliminate these problems, junctionless accumulation mode (JAM) MOSFET was proposed 15–17 .…”

Section: Introductionmentioning

confidence: 99%

Non‐uniform doping dependent electrical parameters of dual‐metal gate all around junctionless accumulation‐mode nanowire FET (DMGAA‐JAM‐NWFET)

Gupta,

Pandey,

Gupta

2024

Int J Numerical Modelling

View full text Add to dashboard Cite

This paper presents an analytical analysis of a dual‐metal gate all around junctionless accumulation‐mode nanowire FET (DMGAA‐JAM‐NWFET) possessing a horizontal‐like non‐uniform doping profile. The 2‐D electrostatic potential distribution is evaluated using Poisson's equation under the applicable boundary conditions. Also, the impact of straggle length parameter and the peak doping concentration upon the device behavior is also examined. For authenticating the obtained analytical outcomes, TCAD simulations were also performed. Both the results were contrasted and found to be in good agreement. The outcomes obtained for non‐uniform doped DMGAA‐JAM‐NWFET are also compared with that of uniformly doped DMGAA‐JAM‐NWFET and finer electrical characteristics were noticed for non‐uniformly doped device.

show abstract

“…The source and drain junctions become close to each other on scaling the device such that the fabrication of such junctions becomes a laborious task. To overcome such pitfall, a device without source/drain junctions are introduced namely junctionless transistors (JLTs) [11][12][13][14][15][16][17]. The JLT basically consists of heavily uniform doped silicon film which has the same doping concentration from source to drain.…”

Section: Introductionmentioning

confidence: 99%

Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

Narula

Agarwal

2020

Semicond. Sci. Technol.

View full text Add to dashboard Cite

A new state of the art double gate junctionless transistor (DGJLT) namely the rectangular core–shell DGJLT (RCS-DGJLT) based common source amplifier circuit is designed to investigate the performance. An RCS-DGJLT device is designed using a visual technology computer aided design tool and look up table-based Verilog-A model has been designed to carry out spice simulation of the circuit. Device simulation of RCS-DGJLT shows the extraordinary performance when compared to conventional DGJLT. The RCS-DGJLT exhibits an OFF current (Ioff ) ∼10−14 A, ON current (Ion ) ∼10−5 A, ON/OFF current ratio (Ion /Ioff ) ∼109, subthreshold slope ∼68.9 mV decade−1 and drain induced barrier lowering ∼52.6 mV V−1. Also, the AC response of RCS-DGJLT exhibits good performance like lower miller capacitances of order 10–16 F, maximum unity gain frequency of 138.8 GHz, transconductance generation efficiency of 40 V−1, and gain-bandwidth product of 25.4 GHz. The common source amplifier circuit using RCS-DGJLT provides the amplification up to 3.3 times which implies gain (Av ) to be 3.3. The low leakage power of 10.4 pW and average power of 31.2 µW of common source amplifier circuit based on RCS-DGJLT shows the greater potential of using the proposed device in analog applications. Also, the complete flow chart of the process used to design an analog circuit based on proposed RCS-DGJLT is discussed. The result shows the potential of using the RCS-DGJLT device in designing high-frequency applications.

show abstract

On performance scaling and speed of junctionless transistors

Cited by 28 publications

References 12 publications

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Non‐uniform doping dependent electrical parameters of dual‐metal gate all around junctionless accumulation‐mode nanowire FET (DMGAA‐JAM‐NWFET)

Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

Contact Info

Product

Resources

About