On Power-Constrained System-On-Chip Test Scheduling Using Precedence Relationships

Harmanani, Haidar M.; Salamy, Hassan

doi:10.1109/newcas.2006.250936

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2020

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“…The simulation is done on MATLAB 14 and LPSOLVE. Comparison of the proposed algorithm with a reference method [19][20][21][22][23][24][25][26] is shown in Table 3 with SoC d695, g1023, p22810, and p93791. Table 3 shows the simulation results for sessionbased test scheduling.…”

Section: Results Discussionmentioning

confidence: 99%

Test Time Reduction Using Power-Aware Dynamic Clock Allocation to Scan Vectors

Parmar

Mehta

2020

Lecture Notes in Electrical Engineering

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As circuit size increases with scale down in technology, the time required to test the circuits also increases. Scheduling of the cores is a very effective technique to reduce the test time of a system-on-chip (SoC) in the given power budget. As the frequency is relative to the power and the test time, by controlling the test clock frequency, the power consumption and the test time per core can be adjusted to yield an optimal solution to the test scheduling problem. In traditional methods, the fixed test clock frequency is applied to all the test vectors of a given core in case of power-aware test scheduling. Whereas in the proposed plan, a power-aware dynamic frequency allocation is done to individual scan vector of the core. Session-based test scheduling scheme is implemented to reduce test time. Results show the improvement up to 58% with session-based test scheduling is achieved over the existing solution for the benchmark SoCs with minor bit and area overhead.

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