2008
DOI: 10.1007/s00165-008-0097-0
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On the correctness of upper layers of automotive systems

Abstract: Formal verification of software systems is a challenge that is particularly important in the area of safety-critical automotive systems. Here, approaches like direct code verification are far too complicated, unless the verification is restricted to small textbook examples. Furthermore, the verification of application logic is of limited use in industrial context, unless the underlying operating system and the hardware are verified, too. This paper introduces a generic model stack, allowing the verification of… Show more

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Cited by 21 publications
(12 citation statements)
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“…In such an approach it remains to be worked out how the introduced models are mapped onto programs that are executed in an infrastructure of the operating systems and middleware. For an example in this direction, see [10].…”
Section: Discussionmentioning
confidence: 97%
“…In such an approach it remains to be worked out how the introduced models are mapped onto programs that are executed in an infrastructure of the operating systems and middleware. For an example in this direction, see [10].…”
Section: Discussionmentioning
confidence: 97%
“…Modeling real-time components has been decomposed into behaviors, their interactions, and priorities on them; reasoning can then occur layer by layer [9], [98]. In general, such approaches allow the verification of all system layers from the correctness proof of the lower layers (i.e., gate-level) to the verification procedure for distributed applications; such an approach has been used to verify automotive systems, a key exemplar of CPS [15]. The practicality and costs of development associated with these approaches are still unknown.…”
Section: Model-based Approachesmentioning
confidence: 99%
“…This direction has been touched for the first time by Botaschanjan et al (2008) though only for upper layer of automotive systems and focused on later verification phases. The first steps towards a methodology for development of verified embedded system have been done in (Botaschanjan et al, 2005;Botaschanjan et al, 2006).…”
Section: Semi-automatic Formal Verificationmentioning
confidence: 99%