On the design and analysis of fault tolerant NoC architecture using spare routers

Chang,; Chiu, -; Lin, Pei-Chun; Liu, Ming

doi:10.1109/aspdac.2011.5722228

Cited by 71 publications

(42 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…During simulation, the links between various routers become faulty and a shorter synapse was initiated to bypass the faulty interconnects. The temporary synapse was formed between router (1) and router (7) to by-pass the faulty interconnect between router (1) and router (2). As shown in the figure, the shorter synapse is bypassing router 2 and router 3 and connecting directly with the old synapse at router 7.…”

Section: Figure 5: Priorities Of "Synap" Packetmentioning

confidence: 99%

Bio-inspired fault tolerant network on chip

2017

View full text Add to dashboard Cite

Section: Figure 5: Priorities Of "Synap" Packetmentioning

confidence: 99%

Bio-inspired fault tolerant network on chip

2017

View full text Add to dashboard Cite

“…Afterwards, the NoC is repaired by activating alternative paths for faulty links. In [20] an NoC with a faulty router or a broken link is repaired using spare routers. The inherent structural redundancy of the NoC architecture is exploited in a cooperative way to detect the faults using BIST [21].…”

Section: Related Workmentioning

confidence: 99%

Transaction-based online debug for NoC-based multiprocessor SoCs

Dehbashi

Fey

2015

Microprocessors and Microsystems

View full text Add to dashboard Cite

a b s t r a c tAs complexity and size of Systems-on-Chip (SoC) grow, debugging becomes a bottleneck for designing IC products. In this paper, we present an approach for online debug of NoC-based multiprocessor SoCs. Our approach utilizes monitors and filters implemented in hardware. Monitors and filters observe and filter transactions at run-time. They are connected to a Debug Unit (DU). Transaction-based programmable Finite State Machines (FSMs) in the DU check assertions online to validate the correct relation of transactions at run-time. The experimental results show efficiency and performance of our approach.

show abstract

“…The dependability issue in the context with NoCs is raising interest in research in the recent years. In [7] an approach for online resource management for MPSoCs is presented and [8] presents a spare router approach. Universal dependability concepts are still less explored.…”

Section: Dependable Soc Communication Architecturesmentioning

confidence: 99%

Invited paper: Design criteria for dependable System-on-Chip architectures

Hollstein

Samman

Jaiswal

et al. 2011

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

View full text Add to dashboard Cite

The rapid improvement of semiconductor technologies is the enabling factor for the design of large-scale Systemon-Chip (SoC) architectures. At the same time the scale-down of feature sizes in silicon technologies brings up new challenges as parameter variations of the transistor devices, an increased vulnerability for wear-out effects during the lifetime of the device and increased sensitivity for soft-errors. The overall system reliability is therefore an important topic to be addressed in the SoC design process as well as economic considerations related to manufacturing yield and lifetime maintainability. The aim of this contribution is to outline implications for the design process and to illustrate the dependability aspects at the example of SoC communication architectures being implemented as Networkson-Chip (NoCs).

show abstract

On the design and analysis of fault tolerant NoC architecture using spare routers

Cited by 71 publications

References 20 publications

Bio-inspired fault tolerant network on chip

Bio-inspired fault tolerant network on chip

Transaction-based online debug for NoC-based multiprocessor SoCs

Invited paper: Design criteria for dependable System-on-Chip architectures

Contact Info

Product

Resources

About