On the Design of a Photonic Network-on-Chip

Abstract

Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the unique capabilities of optical technologies in the on-chip communications infrastructure. Based on these nano-photonic building blocks, we consider a photonic network-on-chip architecture designed to exploit the enormous transmission bandwidths, low latencies, and low power dissipation enabled by data exchange in the optical domain. The novel architectural approach employs a broadband photonic circuit-switched network driven in a distributed fashion by an electronic overlay control network which is also used for independent exchange of short messages. We address the critical network design issues for insertion in chip multiprocessors (CMP) applications, including topology, routing algorithms, path-setup and teardown procedures, and deadlock avoidance. Simulations show that this class of photonic networks-on-chip offers a significant leap in the performance for CMP intrachip communication systems delivering low-latencies and ultra-high throughputs per core while consuming minimal power.

DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing

“…Furthermore, the CMXBar described in the paper requires arbitration, which DCAF does not. The authors in [20] propose a photonic 2D torus network that employs an electrical network for arbitration and flow control. The network is evaluated on a variety of synthetic and scientific benchmarks [4] to show that the hybrid photonic torus network can achieve a factor of 37x improvement in performance per energy spent.…”

“…Most (if not all) of the on-chip photonic networks proposed in the literature so far require arbitration, which is done either electrically [20] or optically [24]. Unfortunately, arbitration is a problem for two reasons -first, it is a cost that must always be paid (the arbitration overhead, in terms of power and performance, is incurred whether or not communication occurs), and second, arbitration is a possible point of failure (if any part of the arbitration network fails, the entire system is rendered useless, making the network less resilient).…”

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip

“…To build a 2D torus topology, a 5×5 optical switch is necessary for each node: one input/output port for each direction (WEST, NORTH, EAST, and SOUTH) and one for the processing element. To remove the need for extra injection and ejection gateways in the switch used in [10], we use the optical switch proposed in [4] shown in Fig. 2.…”

“…However, optical interconnection on chip still faces a number of difficulties. Data buffering and in-flight 1 signal processing are not currently viable at the chip level [10]. Despite these limitations, several researches that take advantage of the unique low power and high bandwidth abilities provided by optical components have been proposed [1,2,4,8,9,12].…”

“…To take full advantage of a wavelength division multiplexing (WDM) technique, which allows the parallel transmission of many optical signals on different wavelengths on a single waveguide, Shacham et al have proposed a circuit switching hybrid photonic network-on-chip (HPNoC) [10]. The architecture consists of a photonic layer, which uses a high-bandwidth circuit switching, controlled by an electrical packet switching layer.…”