On the Reliability of Majority Gates Full Adders

“…In order to tackle this issue, a number of different approaches have been reported in literature, including probabilistic transfer matrix (PTM) method [10][11][12], Bayesian networks (BN) [13][14][15], Markov random field (MRF) [16][17][18][19][20], Monte Carlo (MC) simulation, testing-based method [3], stochastic computation model (SCM) [2,21], probabilistic gate model (PGM) [22][23][24][25], observability-based analysis [26], Boolean difference-based error calculator (BDEC), and correlation coefficient method-(CCM-) based approaches [8,[26][27][28]. In the following, we overview some of these approaches and analyze their pros and cons in terms of accuracy, efficiency, and flexibility with simulation results.…”

Section: Complexity Of Gate-level Reliability Analysismentioning

confidence: 99%

Gate-Level Circuit Reliability Analysis: A Survey

Xiao

Chen

2014

VLSI Design

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Circuit reliability has become a growing concern in today's nanoelectronics, which motivates strong research interest over the years in reliability analysis and reliability-oriented circuit design. While quite a few approaches for circuit reliability analysis have been reported, there is a lack of comparative studies on their pros and cons in terms of both accuracy and efficiency. This paper provides an overview of some typical methods for reliability analysis with focus on gate-level circuits, large or small, with or without reconvergent fanouts. It is intended to help the readers gain an insight into the reliability issues, and their complexity as well as optional solutions. Understanding the reliability analysis is also a first step towards advanced circuit designs for improved reliability in the future research.

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“…The Majority function is a logic circuit that functions as a majority vote to determine the output of the circuits [38]. This function has only odd number of inputs.…”

Section: Carry (Majority) Function-based Hybrid Full Adder Topologiesmentioning

confidence: 99%

“…Its output is equal to "1" when the number of input logic "1" is more than logic "0". Comparing to the XOR implementations of full adder cells, Majority-based full adders are more reliable and robust [38]. Moreover, the bridge style full adder circuits [39] by sharing transistors can operate faster and are smaller than the conventional CMOS full adder circuits.…”

Section: Carry (Majority) Function-based Hybrid Full Adder Topologiesmentioning

confidence: 99%

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

2012

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This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

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On the Reliability of Majority Gates Full Adders

Cited by 59 publications

References 44 publications

Reliability Study of Single Stage Multi-Input Majority Function for QCA

Reliability Study of Single Stage Multi-Input Majority Function for QCA

Gate-Level Circuit Reliability Analysis: A Survey

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

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