On the stability of a 1-bit-quantized feedback system

Hofelt, M.

doi:10.1109/icassp.1979.1170605

Cited by 11 publications

(6 citation statements)

References 5 publications

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“…3. 89. The input amplifier differential pairs that are operating in the V mid ( 3.20) A distributed model can be set-up to calculate at the middle of the ladder the amount of input signal that is modulating the reference voltage source.…”

Section: Reference Ladder Signal Feedthroughmentioning

confidence: 99%

CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters

Plassche¹

2003

254

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Section: Reference Ladder Signal Feedthroughmentioning

confidence: 99%

CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters

Plassche¹

2003

254

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“…The design techniques based on the continuous-time domain have two disadvantages in the model proposed by Breems in [8]. First of all, that linear model is only valid for single-bit CT DSMs [9]. Secondly, the model seems to be more adequate for CT DSMs with high OSR since it has not included the sampling process that occurs inside the loop.…”

Section: Ntf Designmentioning

confidence: 99%

A systematic design methodology for power-optimal design of high-order multi-bit continuous-time Delta-Sigma modulators

Radiom

Craninckx

et al. 2008

Analog Integr Circ Sig Process

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In this paper a systematic design methodology for high-order multi-bit continuous-time Delta-Sigma modulators is proposed. It provides a straightforward method for determining the coefficients of the modulator. The method is illustrated for a 4th-order 4-bit modulator with OSR of 8, while 20 MHz signal bandwidth and 12 bit resolution is achieved. The required GBW of the first integrator is less than 1.5 times the sampling frequency, which greatly reduces the overall power consumption.

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“…In the case of idle patterns, one or more poles are on the unit circle (z = eje) and can be calculated by reducing (5) to:…”

Section: A Idle Patternsmentioning

confidence: 99%

“…For a single-bit quantizer this (real-valued) gain can range from h = 0 if the input signal is extremely large to h = 09 if the input signnl is zero. A sampled quantizer (and a single-bit quantizcr in particular) introduces a phase uncertainty [5] that can have n considerable influence on the overall stability of the system, Modeling of this phase uncertainty allows for a better prcdiction of possible idle patterns (important for the in-bnnd signal-to-quantization error ratio), and calculation of zeroinput stability boundaries for loop-filter parameters. This will be shown in the following sections.…”

Section: Introductionmentioning

confidence: 99%