Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator

Hossain, Md. Maruf; Iizuka, Tetsuya; Nakura, Toru; Asada, Kunihiro

doi:10.1587/transfun.e101.a.410

Cited by 4 publications

(1 citation statement)

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“…We can then select the rank values that give the linear relationship against the input voltage. Although there are different approaches to optimizing the distribution for stochastic ADCs [11], [12], [13], we demonstrate in the paper that ADC with rank-based comparator selection requires a different optimization strategy. We show that ADC performance can be improved significantly without increasing the comparator number with our proposed distribution tuning.…”

Section: Introductionmentioning

confidence: 92%

Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups

Kitamura,

Hisakado,

Wada

et al. 2024

IPSJ Transactions on System LSI Design Methodology

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Statistical element selection has been proposed to solve the offset voltage variation problem for a flash ADC. A calibration method based on order statistics has been proposed for statistical selection that does not require offset voltage measurement. This paper presents a design methodology of flash ADC with such calibration using multiple comparator groups. We validate our proposal with measurement results from test chips fabricated in a commercial 65 nm general-purpose process. Measurement results confirm that rank-based comparator selection achieves a reference-free ADC. Compared to the baseline ADC, where only one group of comparators is used, the ADC with three groups significantly increases the linearity and input range under the same power consumption. As no reference voltage and DACs are required, the proposed ADC design will help realize ADCs in advanced process nodes with lower power consumption.

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Section: Introductionmentioning

confidence: 92%