Optimal FFT architecture selection for ofdm receivers on FPGA

Low Complexity FFT/IFFT Processor Applied for OFDM Transmission System in Wireless Broadband Communication

“…The entire algorithm involves log 2 N stages, where each stage involves N/2 operation units (Butterflies). The computation of the N point FFT via the decimation-in-frequency (DIF) as in the decimation-in-time (DIT) algorithm requires (N/2).log 2 N complex multiplications and N.log 2 N complex additions/subtractions [7]. Based on the same approach, the other fast algorithms: radix-4, radix-8, radix-16, radix-2 2 and split-radix recursively divide the FFT computation into odd and even-half parts and then obtain as many common twiddle factors as possible.…”

“…The subtracted value is multiplied with twiddle factor value W N before being processed into next stage; this computation performed concurrently. The complex multiplication with the twiddle factor requires four real multiplications and two add/subtract operations [4], [7].…”

“…Multiplication with W 16 4 simply can be done by swapping from real to imaginary part and vice versa, followed by changing the sign [7]. The rest of complex multiplications are non-trivial multiplications.…”

A Low Multiplicative Complexity of Proposed FFT/IFFTs Design Applied for OFDM-Based Wireless Communication Systems

“…Moreover, they have fewer glitches. The implementation complexity of non-trivial twiddle factors reduced even further, due to replacement of the complex multiplications by basic operations, such as shift and adds operations [14].…”