Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications

Javaid, Haris; He, Xin; Ignjatovic, Aleksander; Parameswaran, Sri

doi:10.1145/1878961.1878978

Cited by 25 publications

(10 citation statements)

References 14 publications

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“…However, based on our experimental results and recent publications [15], [16], we observe that these cost functions generally exhibit convexity [17]. Therefore, for each component, given its pruned design space (discussed in Section IV), we propose to approximate its cost function with convex piecewise-linear functions.…”

Section: Theorem 2 the Running Time Of Algorithm 1 Is ( Log + Log )mentioning

confidence: 83%

Compositional system-level design exploration with planning of high-level synthesis

Liu

Petracca

Carloni

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed components. In the framework of a compositional methodology for efficient SoC design exploration we present three main contributions: a concise library format for characterization and reuse of components specified in high-level languages like SystemC; an algorithm to prune alternative implementations of a component given the context of a specific SoC design; and an algorithm that explores compositionally the design space of the SoC and produces a detailed plan to run high-level synthesis on its components for the final implementation. The two algorithms are computationally efficient and enable an effective parallelization of the synthesis runs. Through a case study, we show how our methodology returns the essential properties of the design space at the system level by combining the information from the library of components and by identifying automatically those having the most critical impact on the overall design.

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Section: Theorem 2 the Running Time Of Algorithm 1 Is ( Log + Log )mentioning

confidence: 83%

Compositional system-level design exploration with planning of high-level synthesis

Liu

Petracca

Carloni

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…We want the objective function (12a) with |V| optimization variables to be subject to a latency constraint L. Therefore, (12b) comes from (4). In addition, (12c) are the constraints given by (11), and (12d) bounds all optimization variables in the objective function by the worst-case execution time and period as explained in Section III-B. S i and S j (including S in , S out ) are implicit variables which are not in the objective function (12a), but still need to be considered in the optimization procedure.…”

Section: Motivational Examplementioning

confidence: 99%

Resource optimization for CSDF-modeled streaming applications with latency constraints

Liu

Spasić

Zhai

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-In this paper, we study the problem of minimizing the number of processors required for scheduling latencyconstrained streaming applications modeled as CSDF graphs, where the actors of a CSDF are executed as strictly periodic tasks. We formalize the problem and prove that due to the strict periodicity of actors the problem is an integer convex programming problem, that can be solved efficiently by using an existing convex programming solver. We evaluate our solution approach on a set of 13 real-life streaming applications modeled as CSDF graphs and demonstrate that it can reduce the number of processors in more than 52% of the conducted experiments in comparison to an existing approach. I. IntroductionStreaming applications, such as video/audio processing and digital signal processing, have become prevalent in embedded systems. These applications contain ample amount of parallelism which perfectly matches the processing power of MultiProcessor System-on-Chip (MPSoC) platforms. To efficiently program MPSoC platforms, Models-of-Computation (MoCs) are used to specify streaming applications. Prominent examples of MoCs include Synchronous Data Flow (SDF) [1] and its generalization Cyclo-Static Dataflow (CSDF) [2], in which actors representing computation are executed concurrently, thereby naturally exposing parallelism. Furthermore, the strong design-time analyzability of these MoCs makes them suitable for designing performance-constrained embedded systems.Performance constraints of a streaming application are usually imposed on two principle metrics, throughput and latency. For many streaming applications, the latency is the main concern, where latency is the elapsed time between the arrival of a sample to an application and the output of the processed sample by the application. For instance, in video conferencing and automatic pattern recognition applications, a latency that exceeds a certain limit cannot be tolerated. At the same time, the required number of processors to execute the application should be minimized for better resource usage and energy efficiency.A few efforts have been made to deal with latency of streaming applications specified as SDF/CSDF graphs. The authors in [3] studied minimizing latency for SDF graphs, where latency is computed by a state-space traversal which has exponential complexity. Moreover, they assumed that there is no constraint on the number of processors required to schedule an application. However, the number of processors is an important design concern for embedded systems with respect to power consumption and area. In another effort, the authors in [4] and [5] proposed a scheduling framework that schedules acyclic CSDF graphs in a strictly periodic fashion. In this scheduling framework, each CSDF actor executes strictly periodically and meets a given deadline. The periodic execution of actors guarantees a certain

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“…A dynamic programming based algorithm was introduced in [8] to find optimal mapping of tasks on ASIPs of an MPSoC under a period constraint, where custom instructions for ASIPs and intervalbased mapping were considered. The works in [15], [16], [25] considered a pipeline of ASIPs for multimedia applications. They maximized performance improvement per unit area [25] or minimized area under performance constraints [15], [16] while exploring custom instructions and cache configurations.…”

Section: Related Workmentioning

confidence: 99%

Energy-aware synthesis of application specific MPSoCs

Muthukaruppan

Javaid

Mitra

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

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In this paper, we propose a framework for synthesis of application specific MultiProcessor System on Chip (MPSoC) for multimedia applications. Our framework searches for a design with minimum energy consumption under area and period constraints. We simultaneously explore selection of voltagefrequency levels, custom instructions, cache configurations, and task mapping. We propose an optimal algorithm based on prune and search operations to efficiently search the complex design space. We also present a heuristic based on map and customize stages to better handle the exponential complexity of the design space, and rapidly find near-optimal solutions. These algorithms are aided by two estimators that can quickly estimate period and energy consumption of a given design point. Experiments reveal that our framework can reduce energy consumption by 37.9% on an average and 57.1% maximum reduction compared to solutions obtained from a combination of existing techniques.

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Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications

Cited by 25 publications

References 14 publications

Compositional system-level design exploration with planning of high-level synthesis

Compositional system-level design exploration with planning of high-level synthesis

Resource optimization for CSDF-modeled streaming applications with latency constraints

Energy-aware synthesis of application specific MPSoCs

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