Optimization and Comparison of Synchronizers

Reiher, Justin; Greenstreet, Mark R.

doi:10.1109/async49171.2020.00012

Cited by 1 publication

(3 citation statements)

References 17 publications

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“…Since it operates in its saturation region, and so the delivered current is almost independent of the drain-source voltage, altering V out does neither change the current through the TG nor, in consequence, the voltage at V B . Similar disadvantageous effects due to the near-threshold operation of TGs have been reported in [23].…”

Section: A Varying V Ensupporting

confidence: 80%

“…Although these statements hold true for many paths in the plane, it is not generally applicable. For example for those coming too close to the origin V f = V b = 0, both TGs become weak and potentially stop conducting altogether, as also pointed out in [23]. This would not only compromise the dynamic behavior but also lead to a direct transition from memory loop to buffer operation, with a floating internal node in between.…”

Section: Introductionmentioning

confidence: 92%

“…The analyses by Reiher and Greenstreet [23], which focused on the resolution behavior of a synchronizer (four Latches in succession), provide such an example. In a nutshell, the authors discovered that the responsiveness r , denoted as the instantaneous gain λ(t) in their paper, decreases during a clock transition, i.e., that the metastable state is resolved slower.…”

Section: Behavioral Explanationsmentioning

confidence: 99%

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The Hidden Behavior of a D-Latch

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Steininger

Najvirt

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IEEE Trans. Circuits Syst. I

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For clock and data transitions in close temporal proximity, synchronous memory elements potentially enter metastability, which leads to unintended output behavior. Although respective analyses in literature have already derived suitable explanations, almost all of them modeled the control (clock) signal transition with negligible rise/fall time. In modern circuits this assumption is, however, not reasonable any more. In fact, due to a finite slope, intermediate clock signal values have to be considered during a large share of the storage process, while their concrete impact is not yet sufficiently explored. In this paper we thus use static and dynamic considerations to thoroughly investigate the behavior of a latch for arbitrary analog control, data and output values, i.e., during the storage process. Basic circuit considerations allow us to derive a unified model which identifies the latch as a Schmitt Trigger with vastly varying hysteresis. We verify the correctness of our predictions by comparison to analog SPICE simulations. Finally we are able to generalize our findings and thus provide explanations for yet unexplained behavior reported in literature.