Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints

Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism

“…The third type of idle bits is due to imbalanced wrapper chain lengths per core. Hussin et al [16] identified another, fourth type of idle bits, specific to test wrappers that reuse functional interconnect. Their paper also proposes a modification to the wrapper design of [2], that eliminates these idle bits, but adds significant (but in the paper unquantified) area costs.…”

“…They can be prevented by buffering all stimuli and responses. Hussin et al [16] propose a solution in which load and shift registers are used to buffer. This solution requires a significant, but in their paper unquantified, amount of extra silicon area.…”

“…• Type-1: different scan chain lengths within a core [10,20]; • Type-2: scan-in (scan-out) length is not an exact multiple of the input (output) period; • Type-3: maximum scan-in and scan-out lengths are different; • Type-4: the word width of the functional interconnect is not an exact multiple of the number of wrapper chains [2,16].…”

“…In [2,16], these RSDI and RSDO wrapper cells are placed in the middle of the wrapper chains. In contrast, we put them at the extremes of the wrapper chains, such that they do not unnecessarily contribute to the scan lengths, and hence we obtain a (minor) test length improvement over [2,16].…”

Novel Core Test Wrapper Design Supporting Multi-mode Testing of NoC-based SoC

“…A. M. Amory [4,5] proposed the NoC test wrapper design within the constraints of bandwidth and delay and presented simulation results on the ITC benchmark. F. A. Hussin [6,7] described two other NoC wrappers, which were aimed to increase the utilization rate of bandwidth and decrease…”