Optimized Crosstalk Circuit for Long Wire Copper Interconnects using 45nm CMOS Inverter

Bhardwaj, Himani; Jadav, Sunil; Sohal, Harsh; Jain, Shruti

doi:10.1109/wiecon-ece52138.2020.9397927

Cited by 3 publications

(1 citation statement)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This reduces the spacing among interconnects [ 10 ]. With the high signal frequency and small spacing between interconnects, the coupling between the lines has become well known [ 11 , 12 ]. Coupling between signal lines can cause logic failures and timing degradation in digital systems [ 13 ].…”

Section: Introductionmentioning

confidence: 99%

A Reliability System Evaluation Model of NoC Communication with Crosstalk Analysis from Backend to Frontend

et al. 2023

View full text Add to dashboard Cite

Network on chip (NoC) is the main solution to the communication bandwidth of a multi-processor system on chip (MPSoC). NoC also brings more route requirements and is highly prone to errors caused by crosstalk. Crosstalk has become a major design problem in deep-submicron NoC communication design. Hence, a crosstalk error model and corresponding reliable system with error correction code (ECC) are required to make NoC communication reliable. In this paper, a reliability system evaluation model (RSE) of NoC communication with analysis from backend to frontend has been proposed. In the backend, a crosstalk error rate model (CER) is established with a three-wire RLC coupling model and timing constraints. The CER is used to establish functional relations between interconnect spacing, length and signal frequency, and test system reliability. In the frontend, a reliability system performance model (RSP) is established with a CER, reliability method cost and bandwidth. The RSE summarizes the frontend and backend model. In order to verify the RSE model, we propose a reliability system with a hybrid automatic repeat request technique (RSHARQ). Simulation demonstrates that the CER model is close to real circuit design. Through the CER and RSP model, the performance of RSHARQ could be simulated.

show abstract