OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

Marruedo

Franques

et al. 2019

Self Cite

Wireless Network-on-Chip (WNoC) has emerged as a promising alternative to conventional interconnect fabrics at the chip scale. Since WNoCs may imply the close integration of antennas, one of the salient challenges in this scenario is the management of coupling and interferences. This paper, instead of combating coupling, aims to take advantage of close integration to create arrays within a WNoC. The proposed solution is opportunistic as it attempts to exploit the existing infrastructure to build a simple reconfigurable beamforming scheme. Full-wave simulations show that, despite the effects of lossy silicon and nearby antennas, within-package arrays achieve moderate gains and beamwidths below 90 o , a figure which is already relevant in the multiprocessor context.

Section: Opportunistic Beamforming Within a Chip Packagementioning

confidence: 99%

Opportunistic Beamforming in Wireless Network-on-Chip

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

Marruedo

Franques

et al. 2019

Self Cite

“…We easily accommodate 10 Gb/s and reach beyond the coherence bandwidth limit, figures that would be unattainable with conventional coding. Although the static and monolithic nature of the WNoC scenario were already discussed in [24], [40], this is the first work that, to the best of the authors' knowledge, systematically exploits the unique traits of the wireless intra-chip channel. The proposed methodology allows to operate at 10-20 Gb/s with 1-2 pJ/bit, figures that are widely assumed in the literature but that would be otherwise unattainable.…”

Section: Introductionmentioning

confidence: 98%

“…Additionally, 60/90 GHz integrated transceivers specifically designed for WNoC have been tested [20]- [23]. On top of this, a great variety of works have evaluated new topologies and routing protocols [24]- [29] in an attempt to exploit the potential of WNoC at the network level.…”

Section: Introductionmentioning

confidence: 99%

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Timoneda

Franques

et al. 2020

IEEE Trans. Commun.

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Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts, becomes an important bottleneck due to scalability issues. To address this, several works propose the use of mm-wave wireless interconnects for intra-chip communication and demonstrate that, thanks to their low-latency broadcast and system-level flexibility, this new paradigm could break the scalability barriers of current multicore architectures. However, these same works assume 10+ Gb/s speeds and efficiencies close to 1 pJ/bit without a proper understanding on the wireless intra-chip channel. This paper first demonstrates that such assumptions are far from realistic by evaluating losses and dispersion in commercial chips. Then, we leverage the system's monolithic nature to engineer the channel, this is, to optimize its frequency response by carefully choosing the chip package dimensions. Finally, we exploit the static nature of the channel to adapt to it, pushing efficiency-speed limits with simple tweaks at the physical layer. Our methods reduce losses by 47 dB and dispersion by 7.3×, enabling intrachip wireless communications over 10 Gb/s and only 1.9 dB away from the dispersion-free case.

“…Due to its potential, WNoCs have been investigated extensively from the circuit [9], [10], link [11], [12], network [13], [14], and architecture perspectives [15], [16]. However, less attention has been paid to characterizing propagation within the computing package.…”

Section: Introductionmentioning

confidence: 99%

Millimeter-Wave Propagation within a Computer Chip Package

Timoneda

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

Cabellos‐Aparicio

et al. 2018

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Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. The WNoC paradigm has been extensively analyzed from the physical, network and architecture perspectives assuming mmWave band operation. However, there has not been a comprehensive study at this band for realistic chip packages and, thus, the characteristics of such wireless channel remain not fully understood. This work addresses this issue by accurately modeling a flip-chip package and investigating the wave propagation inside it. Through parametric studies, a locally optimal configuration for 60 GHz WNoC is obtained, showing that chip-wide attenuation below 32.6 dB could be achieved with standard processes. Finally, the applicability of the methodology is discussed for higher bands and other integrated environments such as a Software-Defined Metamaterial (SDM).