Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

Abstract

High speed serial interfaces (HSSI) are continually pushed toward operating at higher speed to meet the demand for higher bandwidth. As a result, the timing constraints for HSSI devices get tighter. Consequently, HSSI devices experience issues such as timing jitter and bit-errors. This thesis investigates techniques to speed up bit-error rate (BER) and jitter testing of HSSI devices.This work proposes an oversampling-based transmitter test scheme that accelerates transmitter jitter as well as eye diagram testing through the deployment of a multi-phase bit-error rate test circuit (BERT). The proposed scheme creates parallel BERT elements working in conjunction that are able to digitize the input signal jitter behavior in a multi-phase manner. The more phases we deploy the faster the test is completed.We aim to accurately extract the transmitter jitter in time domain and finish the whole transmitter test within tens of milliseconds. This exceeds the performance of [2], which by itself was an improvement from seconds to 100 ms.ii