'Overturned-stairs' adder trees and multiplier design

Mou, Z.-J.; Jutand, F.

doi:10.1109/12.156536

Cited by 28 publications

(7 citation statements)

References 10 publications

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“…Overturned-Stairs (OTS) Multiplier: This is a straight-forward implementation of the multiplier presented by Mou [18]. It uses the suggested branches and connectors, and achieves a worst case path of .…”

Section: A Multiplier Schemesmentioning

confidence: 99%

Toward architecture-based test-vector generation for timing verification of fast parallel multipliers

Eriksson

Larsson-Edefors

Eckerbert

2006

IEEE Trans. VLSI Syst.

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Fast parallel multipliers that contain logarithmic partial-product reduction trees pose a challenge to simulation-based high-accuracy timing verification, since the reduction tree has many reconvergent signal branches. However, such a multiplier architecture also offers a clue as how to attack the test-vector generation problem. The timing-critical paths are intimately associated with long carry propagation. We introduce a multiplier test-vector generation method that has the ability to exercise such long carry propagation paths. Through extensive circuit simulation and static timing analysis, we evaluate the quality of the test vectors that result from the new method. Especially for fast multipliers with a pronounced carry propagation, the timing-critical vectors manage to stimulate a path, which has a delay that comes close to the true worst case delay. We investigate the complexity and run-time for the test-vector generation, and derive timing-critical vectors up to a factor word length of 54 bits.

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Section: A Multiplier Schemesmentioning

confidence: 99%

Toward architecture-based test-vector generation for timing verification of fast parallel multipliers

Eriksson

Larsson-Edefors

Eckerbert

2006

IEEE Trans. VLSI Syst.

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“…This can increase the delays and become a limiting factor in the final implementation. Reduction trees that are more regular include overturned stairs-reduction tree [215] and the high performance multiplier (HPM) tree [216].…”

Section: Tree Accumulation Of Partial Productsmentioning

confidence: 99%

Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

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Finite-length impulse response (FIR) filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to infinite impulse response (IIR) filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.One technique to reduce the number of multipliers is to use cascaded subfilters with lower complexity to achieve the desired specification, known as frequency-response masking (FRM). One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient v vi Abstract pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M . This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alt...

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“…The overturned-stairs tree [9], which has a regular layout and the same performance as the Wallace tree when the data word length is less than 19, is used in the design of the complex multipliers [lo].…”

Section: Complex Multipliermentioning

confidence: 99%

A pipeline FFT processor

Wanhammar²

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

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'Overturned-stairs' adder trees and multiplier design

Cited by 28 publications

References 10 publications

Toward architecture-based test-vector generation for timing verification of fast parallel multipliers

Toward architecture-based test-vector generation for timing verification of fast parallel multipliers

Techniques for Efficient Implementation of FIR and Particle Filtering

A pipeline FFT processor

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