2019
DOI: 10.1002/sdtp.13215
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P‐60: An 8Gbps Receiver for 8K Large‐Size Display

Abstract: An 8Gbps receiver is implemented in 1.2V 0.11um high-voltage CMOS process for 8K 120Hz large-size display. Signal integrity is also improved to achieve maximum data rate of 8Gbps, 6Gbps over prototype channels for 65-inch display, 85-inch double-side driving display respectively. The measured bit error rate is below 1E-9 for PRBS-18.

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Cited by 2 publications
(2 citation statements)
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“…The sub-pixel size was 3.4 µm × 10.2 µm, the diagonal display size was 0.8 inch, and the display resolution was 1,920 × 540, which resulted in ∼ 2,490 pixels per inch (ppi). To drive the logic circuits and OLED pixels, 1.8 and 7 V transistor processes were adopted [9][10][11][12]. After the backplane was fabricated, it was successively cleaned with isopropyl alcohol and acetone, and dried in a vacuum oven at 120°C.…”
Section: Methodsmentioning
confidence: 99%
“…The sub-pixel size was 3.4 µm × 10.2 µm, the diagonal display size was 0.8 inch, and the display resolution was 1,920 × 540, which resulted in ∼ 2,490 pixels per inch (ppi). To drive the logic circuits and OLED pixels, 1.8 and 7 V transistor processes were adopted [9][10][11][12]. After the backplane was fabricated, it was successively cleaned with isopropyl alcohol and acetone, and dried in a vacuum oven at 120°C.…”
Section: Methodsmentioning
confidence: 99%
“…The on-chip bit error tester is used to evaluate the signal quality and the receive ability of RX (with equalization) [4]. Here, the iSP protocol can support bit error detection, which counts the number of error bits in the iSP data stream until it is greater or equal to the threshold.…”
Section: Bit Error Detectionmentioning
confidence: 99%