Packing Multiple Types of Cores for Energy-Optimized Heterogeneous Hardware-Software Co-Design of Moldable Streaming Computations

Abstract

For fixed-application scenarios in embedded soft-realtime computing, the ideal (w.r.t. energy consumption) heterogeneous multi-core CPU design within given chip dimensions can be configured by composing it from given pre-layouted, rectangular chip submodules for each of a number K > 1 of core types, where K in practice is a small constant. For example, K = 2 in traditional ARM big.LITTLE designs. Nevertheless, even better solutions might be achieved for K>2, and many feasible combinations can exist. For this purpose, we investigate finding all combinations of instances of K > 1 different types of given axis-parallel rectangles that can be packed within a given fixed-size 2D rectangle, and we propose two new packing heuristics: the corner heuristic for K ≤ 4, and the onion heuristic for larger K. Both heuristics strive to pack cores of the same type close together, to simplify implementation of on-chip bus and shared cache structures. The core combinations can be used in co-optimizing chip configuration, task mapping and scheduling for stream processing applications. We evaluate the corner heuristic for a number of different types of ARM softcores and chip dimensions, and show that it outperforms strip packing techniques from the literature and yields similar results to an advanced rectpack heuristic allowing rotation, though these do not try to pack similar cores closely. INDEX TERMSPacking rectangles, heterogeneous multi-core CPU, design space exploration, hardwaresoftware co-design VOLUME 4, 2016