PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems

Kokolis, Apostolos; Skarlatos, Dimitrios; Torrellas, Josep

doi:10.1109/hpca.2019.00012

Cited by 32 publications

(11 citation statements)

References 39 publications

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“…Wear leveling has been studied extensively for Flash-based storage devices [32][33][34][35][36]. In these methods, the wear-leveling algorithms usually keep track of the storage blocks and remap those blocks that are written heavily in a given time Article Title quanta to the lowest wear-out blocks.…”

Section: Wear Levelingmentioning

confidence: 99%

Challenges and future directions for Energy, Latency, and Lifetime Improvements in NVMs

Kargar

Nawab

2022

Preprint

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Recently, Non-Volatile Memory (NVM) technology has revolutionized the landscape of memory systems. With many advantages, such as non volatility and near zero standby power consumption, these byte-addressable memory technologies are taking the place of DRAMs. Nonetheless, they also present some limitations, such as limited write endurance, which hinders their widespread use in today’s systems. Furthermore, adjusting current data management systems to embrace these new memory technologies and all their potential is proving to be a nontrivial task. Because of this, a substantial amount of research has been done, from both the database community and the storage systems community, that tries to improve various aspects of NVMs to integrate these technologies into the memory hierarchy. In this tutorial we survey state-of-the-art work on deploying NVMs in database and storage systems communities and the ways their limitations are being handled within these communities. In particular, we focus on the challenges that are related to high energy consumption, low write endurance and extending the lifetime of NVM devices.

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Section: Wear Levelingmentioning

confidence: 99%

Challenges and future directions for Energy, Latency, and Lifetime Improvements in NVMs

Kargar

Nawab

2022

Preprint

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“…Specifically, TEMPO [12] uses PTE page walk requests that miss in the cache hierarchy to prefetch the cache line that caused the page walk to LLC from main memory. PageSeer [35] uses page walk information to swap pages in a DRAM-NVM hybrid main memory system. Cloak is different because it hides the higher read latency of NVM-based LLCs.…”

Section: Other Related Workmentioning

confidence: 99%

Cloak

Kokolis

Mantri²,

Ganapathy³

et al. 2022

Proceedings of the 36th ACM International Conference on Supercomputing

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The increased memory demands of workloads are putting high pressure on Last Level Caches (LLCs). In general, there is limited opportunity to increase the capacity of LLCs due to the area and power requirements of the underlying SRAM technology. Interestingly, emerging Non-Volatile Memory (NVM) technologies promise a feasible alternative to SRAM for LLCs due to their higher area density. However, NVMs have substantially higher read and write latencies, which offset their density benefit. Although researchers have proposed methods to tolerate NVM's higher write latency, little emphasis has been placed on the critical NVM read latency.To address this problem, this paper proposes Cloak. Cloak exploits page-level data reuse in the LLC, to hide NVM read latency. Specifically, on certain L1 DTLB misses, Cloak transfers LLC-resident data belonging to the TLB-missing page from the LLC NVM array to a set of small SRAM Page Buffers that will service subsequent requests to this page. Further, to enable the high-bandwidth, lowlatency transfer of lines of a page to the page buffers, Cloak uses an LLC layout that accelerates the discovery of LLC-resident cache lines from the page. We evaluate Cloak with full-system simulations of a 4-core processor across 14 workloads. We find that, on average, a machine with Cloak is faster than one with an SRAM LLC by 23.8% and one with an NVM-only LLC by 8.9%-in both cases, with negligible change in area. Further, Cloak reduces the ED 2 metric relative to these designs by 39.9% and 17.5%, respectively. CCS CONCEPTS• Hardware → Non-volatile memory.

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“…Specifically, TEMPO [12] uses PTE page walk requests that miss in the cache hierarchy to prefetch from main memory to the LLC, the cache line that caused the page walk. PageSeer [34] uses page walk information to swap pages in a DRAM-NVM hybrid main memory system. Cloak is different from these approaches.…”

Section: Other Related Workmentioning

confidence: 99%

A Method for Hiding the Increased Non-Volatile Cache Read Latency

Kokolis¹,

Mantri²,

Ganapathy³

et al. 2021

Preprint

Self Cite

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The increased memory demands of workloads is putting high pressure on Last Level Caches (LLCs). Unfortunately, there is limited opportunity to increase the capacity of LLCs due to the area and power requirements of the underlying SRAM technology. Interestingly, emerging Non-Volatile Memory (NVM) technologies promise a feasible alternative to SRAM for LLCs due to their higher area density. However, NVMs have substantially higher read and write latencies, which offset their area density benefit. Although researchers have proposed methods to tolerate NVM's increased write latency, little emphasis has been placed on reducing the critical NVM read latency.To address this problem, this paper proposes Cloak. Cloak exploits data reuse in the LLC at the page level, to hide NVM read latency. Specifically, on certain L1 TLB misses to a page, Cloak transfers LLC-resident data belonging to the page from the LLC NVM array to a set of small SRAM Page Buffers that will service subsequent requests to this page. Further, to enable the high-bandwidth, low-latency transfer of lines of a page to the page buffers, Cloak uses an LLC layout that accelerates the discovery of LLC-resident cache lines from the page. We evaluate Cloak with full-system simulations of a 4-core processor across 14 workloads. We find that, on average, Cloak outperforms an SRAM LLC by 23.8% and an NVM-only LLC by 8.9%-in both cases, with negligible additional area. Further, Cloak's ED 2 is 39.9% and 17.5% lower, respectively, than these designs.

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PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems

Cited by 32 publications

References 39 publications

Challenges and future directions for Energy, Latency, and Lifetime Improvements in NVMs

Challenges and future directions for Energy, Latency, and Lifetime Improvements in NVMs

Cloak

A Method for Hiding the Increased Non-Volatile Cache Read Latency

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