Parallel strategies for SIDH: Towards computing SIDH twice as fast

Cervantes-Vázquez, Daniel; Ochoa-Jiménez, Eduardo; Rodríguez-Henríquez, Francisco

doi:10.1109/tc.2021.3080139

Cited by 3 publications

(15 citation statements)

References 14 publications

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“…For this setting, we utilize the equation C PCP * K to construct strategies. To achieve better speed-up, we consider the optimization of [COR22] and modify PCS to accommodate such optimization.…”

Section: Multi-core Implementation Using Pcsmentioning

confidence: 99%

“…We first describe the speed-up technique of Cervantes-Vázquez et al [COR22] for multi-core platforms. Some isogeny-based protocols require computing a point R from other points, e.g., R ← P + [m]Q for 0 ≤ m < e , before passing it as an input for isogeny computation.…”

Section: Modifying Pcs For Speed-upmentioning

confidence: 99%

“…The optimization of [COR22] significantly reduces the isogeny computation time. However, it can be further reduced, as we can see that the isogeny evaluations performed on R are done serially and the computation does not utilize all available cores.…”

Section: Modifying Pcs For Speed-upmentioning

confidence: 99%

“…Looking at the experimental results, the theoretical costs of optimal strategies under PCP are up to 24%, 40%, and 51% cheaper than the costs of optimal strategies of [FJP14] when the number of cores is two, four, and eight, respectively. And when implementing the computation on a three-core platform using the techniques of [HK18] along with other optimizations, Cervantes-Vázquez et al [COR22] could achieve more than 35% speed-up in the execution time compared to the serial implementation. These results clearly show an impact on the speeding-up of isogeny computation for multi-core platforms at the strategy-level.…”

Section: Introductionmentioning

confidence: 99%

“…We use OpenMP for multi-threading with extensive techniques to handle synchronization among cores. Moreover, we include an optimization of [COR22] and modify the scheduling algorithm of [PSH22] to take advantage of this optimization. As a result, we are able to obtain speed-ups of up to 12.53%, 12.57%, and 14.36% when compared to [COR22] using two, three, and four cores, respectively.…”

Section: Introductionmentioning

confidence: 99%

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Vectorized and Parallel Computation of Large Smooth-Degree Isogenies using Precedence-Constrained Scheduling

Phalakarn¹,

Suppakitpaisarn²,

Rodríguez-Henríquez³

et al. 2023

TCHES

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Strategies and their evaluations play important roles in speeding up the computation of large smooth-degree isogenies. The concept of optimal strategies for such computation was introduced by De Feo et al., and virtually all implementations of isogeny-based protocols have adopted this approach, which is provably optimal for single-core platforms. In spite of its inherent sequential nature, several recent works have studied ways of speeding up this isogeny computation by exploiting the rich parallelism available in vectorized and multi-core platforms. One obstacle to taking full advantage of this parallelism, however, is that De Feo et al.’s strategies are not necessarily optimal in multi-core environments. To illustrate how the speed of vectorized and parallel isogeny computation can be improved at the strategylevel, we present two novel software implementations that utilize a state-of-the-art evaluation technique, called precedence-constrained scheduling (PCS), presented by Phalakarn et al., with our proposed strategies crafted for these environments. Our first implementation relies only on the parallelism provided by multi-core processors. The second implementation targets multi-core processors supporting the latest generation of the Intel’s Advanced Vector eXtensions (AVX) technology, commonly known as AVX-512IFMA instructions. To better handle the computational concurrency associated with PCS, we equip both implementations with extensive synchronization techniques. Our first implementation outperforms the implementation of Cervantes-Vázquez et al. by yielding up to 14.36% reduction in the execution time, when targeting platforms with two- to four-core processors. Our second implementation, equipped with four cores, achieves up to 34.05% reduction in the execution time compared to the single-core implementation of Cheng et al. of CHES 2022.

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Section: Multi-core Implementation Using Pcsmentioning

confidence: 99%

Section: Modifying Pcs For Speed-upmentioning

confidence: 99%

Section: Modifying Pcs For Speed-upmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Vectorized and Parallel Computation of Large Smooth-Degree Isogenies using Precedence-Constrained Scheduling

Phalakarn¹,

Suppakitpaisarn²,

Rodríguez-Henríquez³

et al. 2023

TCHES

View full text Add to dashboard Cite

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A New Adaptive Attack on SIDH

Fouotsa

Petit

2022

Topics in Cryptology – CT-RSA 2022

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