Parasitic Gate Capacitance Model for Triple-Gate FinFETs

Rodriguez, Silvestre Salas; Tinoco, J. C.; Martinez-Lopez, A. G.; Alvarado, J.; Raskin, Jean‐Pierre

doi:10.1109/ted.2013.2282629

Cited by 49 publications

(21 citation statements)

References 18 publications

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“…Besides, the unique gate structure leads to increased gate capacitance and also to more components when modeling the parasitic capacitance and resistance compared to the planar devices. 19,20 These capacitance and resistance values are crucial since the inaccuracy caused during extracting R and C parasitic will lead to mis-characterization and under/over-estimated design margins. Figure 4 shows an example of how FinFET parasitic capacitance is accounted for a 2-finger device.…”

Section: Device Modelsmentioning

confidence: 99%

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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It has been almost a decade since FinFET devices were introduced to full production; they allowed scaling below 20 nm, thus helping to extend Moore's law by a precious decade with another decade likely in the future when scaling to 5 nm and below. Due to superior electrical parameters and unique structure, these 3-D transistors offer significant performance improvements and power reduction compared to planar CMOS devices. As we are entering into the sub-10 nm era, FinFETs have become dominant in most of the high-end products; as the transition from planar to FinFET technologies is still ongoing, it is important for digital circuit designers to understand the challenges and opportunities brought in by the new technology characteristics. In this paper, we study these aspects from the device to the circuit level, and we make detailed comparisons across multiple technology nodes ranging from conventional bulk to advanced planar technology nodes such as Fully Depleted Silicon-on-Insulator (FDSOI), to FinFETs. In the simulations we used both state-of-art industry-standard models for current nodes, and also predictive models for future nodes. Our study shows that besides the performance and power benefits, FinFET devices show significant reduction of short-channel effects and extremely low leakage, and many of the electrical characteristics are close to ideal as in old long-channel technology nodes; FinFETs seem to have put scaling back on track! However, the combination of the new device structures, double/multi-patterning, many more complex rules, and unique thermal/reliability behaviors are creating new technical challenges. Moving forward, FinFETs still offer a bright future and are an indispensable technology for a wide range of applications from high-end performance-critical computing to energy-constraint mobile applications and smart Internet-of-Things (IoT) devices.

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Section: Device Modelsmentioning

confidence: 99%

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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“…20 shows the gate capacitance of TTMSON with different inclinations as a function of V gs . The gate capacitance is calculated by estimating the extrinsic five‐capacitance components and two internal capacitance components [28, 29]. It can be seen from Fig.…”

Section: Resultsmentioning

confidence: 99%

Analytical modelling and performance analysis of gate‐ and channel‐engineered trapezoidal trigate MOSFET

Shora

Khanday

2019

IET Circuits, Devices & Systems

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Here, the authors propose an analytical model to evaluate the performance of an advanced trigate MOSFET structure called trapezoidal trigate MOSFET on silicon-on-nothing (TTMSON). The model is based on the solution of Poisson's partial differential equation in three dimensions. The expression for potential distribution has been used to model other device parameters like electric field distribution, quantum inversion charge, and threshold voltage. The TTMSON device immunity to various short channel effects (SCEs), such as drain-induced barrier lowering (DIBL) and sub-threshold swing, has been examined. A detailed analysis of the gate and channel engineering techniques like dual material gate, graded channel, and dual material gate with graded channel has also been carried out to choose the best device structural configuration for enhancing the device performance and mitigating SCEs in nano-regime. In addition, the effect of inclination angle on different performance parameters has been considered. The proposed analytical model of TTMSON has been verified by comparing the model results with the simulation results using the numerical device simulator ATLAS.

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“…Although it is out of the scope of this paper, this approach can be generalized to other architectures such as nanowires [28], [29] or FinFET [30], [31]. Finally, this model is simple and efficient enough for implementation in the MASTAR platform.…”

Section: Discussionmentioning

confidence: 99%

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Hiblot

Rafhay

Bœuf

et al. 2015

IEEE Trans. Electron Devices

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In this paper, the main MOSFET parasitic capacitances of planar devices (i.e., bulk, Fully depleted silicon-on-insulator (FDSOI), and planar double gate) are computed using two successive conformal mapping transforms. First, the structure is mapped to the real axis of the complex plane, and then the second transform, deduced directly from the Schwarz-Christoffel theorem, reduces the capacitance to the trivial parallel electrodes case. This second step involves elliptic integrals, which provide a generic expression for all parasitic capacitances. This method is later compared against other models based on conformal mapping. Finally, the results are validated with finite-element method simulations of the inner and outer fringe capacitances in different architectures, including metallic contacts and raised and faceted junctions.Index Terms-CMOS, compact model, conformal mapping, electrostatic, elliptic integrals, Model for Assessment of CMOS Technologies and Roadmaps (MASTAR), MOSFET, parasitic capacitance, roadmap.

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Parasitic Gate Capacitance Model for Triple-Gate FinFETs

Cited by 49 publications

References 18 publications

Back to the Future: Digital Circuit Design in the FinFET Era

Back to the Future: Digital Circuit Design in the FinFET Era

Analytical modelling and performance analysis of gate‐ and channel‐engineered trapezoidal trigate MOSFET

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

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