Parity-Check Polar Coding for 5G and Beyond

Abstract

In this paper, we propose a comprehensive Polar coding solution that integrates reliability calculation, rate matching and parity-check coding. Judging a channel coding design from the industry's viewpoint, there are two primary concerns: (i) low-complexity implementation in applicationspecific integrated circuit (ASIC), and (ii) superior & stable performance under a wide range of code lengths and rates. The former provides cost-& power-efficiency which are vital to any commercial system; the latter ensures flexible and robust services. Our design respects both criteria. It demonstrates better performance than existing schemes in literature, but requires only a fraction of implementation cost. With easilyreproducible code construction for arbitrary code rates and lengths, we are able to report "1-bit" fine-granularity simulation results for thousands of cases. The released results can serve as a baseline for future optimization of Polar codes. 1

An Asymmetric Adaptive SCL Decoder Hardware for Ultra-Low-Error-Rate Polar Codes

“…One FPGA board can be up to 7000 times faster than a CPU core. • Flexibility: The emulation platform supports CA-Polar (up to 24 CRC bits), PC-Polar [3] (as specified by 3GPP), various rate-matching schemes, list sizes, code lengths and code rates. All these can be configured by the server on the fly.…”

“…To improve error-correction performance at short or moderate lengths, SC list (SCL) decoding is proposed by keeping L codeword candidates. Concatenated with cyclic redundancy check (CRC) [2] or parity check (PC) [3] bits, the error-correction performance can be further improved.…”

“…SC/SCL cycles are half of the sum run time for two packets due to pipelining 3. SC employs syndrome-check acceleration[?…”

A 5.16Gbps decoder ASIC for Polar Code in 16nm FinFET

“…For cyclic redundancy check (CRC) aided SCL (CA-SCL) [13], the most reliable path that passes the CRC is selected as the decoding output. For parity-check SCL (PC-SCL) [14], each parity bit is decided by its parity function rather than by the LLR.…”

“…Flexible decoder supports variable list size and code length, with upper limit L max = 8 and N max = 2 14 . The architecture of flexible decoder is shown in Fig.…”