PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

Abstract

Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications. Network-on-chip (NoC) has become a very promising interconnection structure because of its good scalability, predictable interconnect length and delay, high bandwidth, and reusability. However, the most available packet routing NoC may not be the perfect solution for high-end heterogeneous multi-core real-time systems-on-chip (SoC) because of the excessive latency and cache cost overhead. Moreover, circuit switching is limited by the scale, connectivity flexibility, and excessive overhead of fully connected systems. To solve the above problems and to meet the need for low latency, high throughput, and flexibility, this paper proposes PCCNoC (Packet Connected Circuit NoC), a low-latency and low-overhead NoC based on both packet switching (setting-up circuit) and circuit switching (data transmission on circuit), which offers flexible routing and zero overhead of data transmission latency, making it suitable for high-end heterogeneous multi-core real-time SoC at various system scales. Compared with typically available packet switched NoC, our PCCoC sees 242% improved performance and 97% latency reduction while keeping the silicon cost relatively low.

PaCHNOC: Packet and Circuit Hybrid Switching NoC for Real-Time Parallel Stream Signal Processing

“…To evaluate the performance of different NoCs, a baseline, VCS [ 35 ], CIMA [ 24 ], and PCCNOC [ 6 ] are used for experiment. The parameters of these NoCs are mentioned in Table 3 .…”

“…PCCNOC [ 6 ] is our previous-generation work that establishes circuits through packet switching and then transmits data through circuits. It is characterized by making full use of the flexibility of packet-switched networks and the reliability of circuit switching, and has obvious performance advantages in the case of large data transmission.…”

“…Secondly, we focus our attention to real benchmark traffic. Snipersim 6.1 [ 37 ] was used to trace real benchmark traffic, and the router and network interface of VCS [ 35 ], CIMA [ 24 ], PCCNOC [ 6 ], and PaCHNOC were implemented on Snipersim. We selected five PARSEC [ 38 ] benchmark applications (viz.…”

“…Figure 1 illustrates an exemplary MPSoC platform, consisting of CPUs, DSPs, ASICs, and ASIPs (Application Specific Instruction-set Processor). We previously proposed a hybrid switching method PCCNOC [ 6 ] using packet-connected circuit. The PCCNOC proposed an approach presenting a temporally locked circuit, resulting in reduced latency and zero buffer cost.…”

“…Hybrid switching proposed achieves the advantages techniques on both circuit-switched low latency data transfer and packet-switched low channel setup cost [ 13 ]. In PCCNOC [ 6 ], packet-switched channel transfers circuit configuration vector, while circuit-switched channel transfers task data propagates on energy-efficiency and short latency due to buffer-free and no additional arbitration after locking the circuit. Circuit-switched channels release resources via unlocking the paths after completed transmission.…”