PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register Files

Namazi, Alireza; Abdollahi, Meisam

doi:10.1109/dsd.2017.90

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PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register Files

Cited by 5 publications

References 18 publications

Design and Implementation of Fault Tolerant LZW for Reliable Data Compression Using Verilog HDL

Design and Implementation of Fault Tolerant LZW for Reliable Data Compression Using Verilog HDL

Clock Gating Implementation on commercial Field Programmable Gate Array (FPGA)

Turn-aware Application Mapping using Reinforcement Learning in Power Gating-enabled Network on Chip

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