Performance analysis of CLEFIA and PRESENT lightweight block ciphers

Jangra, Monika; Singh, Buddha

doi:10.1080/09720529.2019.1695900

Cited by 12 publications

(2 citation statements)

References 8 publications

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“…The memory usage and throughput factors are discussed for all the light-weight block ciphers in the Industrial WSN system. Jangra et al [24] explains the implementation of the PRESENT and CLEFIA light-weight block ciphers in python and analyzes the performance metrics. The metrics like throughput, resource utilization, and security strength are discussed for both the ciphers.…”

Section: Related Workmentioning

confidence: 99%

Light-Weight Present Block Cipher Model for IoT Security on FPGA

Bharathi¹,

Parvatham²

2022

Intelligent Automation &Amp; Soft Computing

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The Internet of Things (IoT) plays an essential role in connecting a small number of billion devices with people for diverse applications. The security and privacy with authentication are challenging work for IoT devices. A lightweight block cipher is designed and modeled with IoT security for real-time scenarios to overcome the above challenges. The light-weight PRESENT module with the integration of encryption (E)-decryption (D) is modeled and implemented on FPGA. The PRESENT module has 64-bit data input with 80/128/256-bit symmetric keys for IoT security. The PRESENT module performs16/32/64 round operations for state register and key updation. The design mainly uses Substitution-permutation (SP) network for state updation. The permutation layer is used to create more diffusion and confusion in the state for unauthorized access. The results and analysis of the PRESENT-80/128/256 are designed using Verilog-HDL with Xilinx Environment and implemented on Artix-7 FPGA. The PRESENT-80/128/256 module is compared with similar recent works with performance improvements. Similarly, the proposed work is compared with different light-weight algorithms with improvements for better security in IoT devices. The proposed PRESENT-256 module with 64-rounds on Artix-7 FPGA utilizes less than 2% Chip area (Slices and LUTs), works at 412.4 MHz frequency, and consumes 192 mW total power and 0.58 Mbps/slice of hardware efficiency.

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Section: Related Workmentioning

confidence: 99%

Light-Weight Present Block Cipher Model for IoT Security on FPGA

Bharathi¹,

Parvatham²

2022

Intelligent Automation &Amp; Soft Computing

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“…More recently, it was reported that AES may not act as an ultimate choice for the IoT environment, due to the fact that it requires extensive hardware resources [43]. The software evaluation of [44] compared Present and Celfia in terms of security strength, performance, and resource utilization, demonstrating that Present requires fewer memory footprints than Celfia, due to the fact that the latter utilizes two S-boxes; however, Present requires more encryption time and average CPU cycles than Celfia.…”

Section: Development and Evaluationmentioning

confidence: 99%

Software Design and Experimental Evaluation of a Reduced AES for IoT Applications

2021

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IoT devices include RFID tags, microprocessors, sensors, readers, and actuators. Their main characteristics are their limited resources and computing capabilities, which pose critical challenges to the reliability and security of their applications. Encryption is necessary for security when using these limited-resource devices, but conventional cryptographic algorithms are too heavyweight and resource-demanding to run on IoT infrastructures. This paper presents a lightweight version of AES (called LAES), which provides competitive results in terms of randomness levels and processing time, operating on GF(24). Detailed mathematical operations and proofs are presented concerning LAES rounds design fundamentals. The proposed LAES algorithm is evaluated based on its randomness, performance, and power consumption; it is then compared to other cryptographic algorithm variants, namely Present, Clefia, and AES. The design of the randomness and performance analysis is based on six measures developed with the help of the NIST test statistical suite of cryptographic applications. The performance and power consumption of LAES on a low-power, 8-bit microcontroller unit were evaluated using an Arduino Uno board. LAES was found to have competitive randomness levels, processing times, and power consumption compared to Present, Clefia, and AES.

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