Performance analysis of cluster based 3D routing algorithms for NoC

Abstract

In the nano scaled transistors integration era, interconnection of IP blocks and data exchange among the IP blocks are crucial concerns in System on Chip (SoC). Networkon-Chip (NoC) is an on-chip communication methodology proposed to resolve the increased interconnection problems in SoC. In deep sub-micron regime, 3D NoC becomes an emerging research area in recent years as the three dimensional (3D) integrated circuits (ICs) can offer shorter interconnection wire and dissipate lesser power. Major area of the 3D NoC research is network topology and routing techniques. In this paper, we present an NS-2 (Network Simulator) simulation environment for two 3D network topologies (GBT and CBT) and cluster based routing algorithms. Simulation results are reported.Simulation results about the relationship between switch buffer size, injected traffic load, packet delay, packet drop probability and energy dissipation are analyzed. On comparing CBT with GBT, a significant performance improvement is demonstrated.

An optimised 3D topology for on-chip communications

“…In this section, we present a 3D NoC topology, namely 3D RNT as shown in Figure 1, where only three layers are considered for experimental analysis at ease even though n layers can be accommodated in the topology [4,28,29]. The 3D topology is derived from 2D WK recursive network topology of W(4, 2) without changing its properties where only four additional flipping links are added in each layer except in top and bottom layers of the 3D topology.…”

Performance and cost metrics analysis of a 3D NoC topology using network calculus

“…Analytical models are being considered recently to evaluate the traffic related parameters and they allow the designers to investigate trade-off between different parameters rapidly so as to improve the performance of the 3D NoC topology [12,13]. Among the many 3D NoC topologies proposed in [7,8,9], the 3D recursive network topology (3D RNT) has been identified as an appropriate topology for 3D NoC. The topology offers a high degree of scalability, higher performance and well suited for modular approach and to implement heterogeneous, distributed systems involving a large number of IP blocks.…”

“…Network calculus is an analytical model that computes the input and output arrival curves, end-to-end delay bounds, buffer size of the switch and other performance metrics of 2D mesh on-chip interconnect and the results of the model are compared against simulation results in the papers [13,17]. In the papers [7,8], 3D NoC topologies are evaluated using Network Simulator-2 (NS-2), an open source simulator where five traffic source-sink pairs are selected randomly and the simulation output for the end-to-end delay is observed by varying both injected data rate and buffer size of the switches.…”

“…A recursive network is denoted as K (l, 4, t) where l is the number of tiers/layers and t is the levels, l and t ≥1. If l=1, the topology is 2D recursive network topology (2D RNT) and l >1, the topology is 3D RNT is shown in Fig.1 [7][8][9][10][11].…”

“…In this paper, we have taken K (3,4,2) as our topology [11]. In the topology, each layer has four clusters which are formed by grouping four nodes with one node as cluster head (CH) [7,8].…”