Performance analysis of HFDI computing algorithm in intelligent networks

Budati, Anil Kumar; Polipalli, Trinatha Rao

doi:10.1080/1206212x.2017.1396424

Cited by 13 publications

(4 citation statements)

References 8 publications

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“…The 4-bit CSA is proven for less power with help of FinFET (Ravi Sankar et al, 2018). Inexact registering (Mazahir et al, 2019) has presented new roads of equipment advancements in advanced plans for computationally broad applications, which can bear bargaining the precision in the conventional math as a compromise for improved force, speed or territory (Budati and Polipalli, 2019;Kumar and Rao, 2019). IJIUS 10,1 3.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA

Kumar¹,

Rangaraju²

2021

IJIUS

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PurposeFinite impulse response (FIR) digital filters are a general element in several digital signal processing (DSP) systems. In VLSI platform, FIR is a developing filter because the complexity of design grows with the length of the FIR filter and also it has less latency. Generally, the FIR filter is designed dominated by the multiplier and adder. The conventional FIR filters occupy more area because of several numbers of adders and multipliers for filter designs.Design/methodology/approachTo overcome this issue, the Vedic Multiplier (VM) and Moore-based LoopBack Adder (MLBA) approach-based optimal FIR filter were designed in this research. Normally, the coefficient has been generated manually, which performs the FIR filter operation. So, the coefficient was generated from the MATLAB filter design and analysis tool. All pass coefficient was introduced in this research, which performs the processing element (PE). The VM approach was utilized in the PE to multiply the filter inputs and coefficients. This research employs the Moore-based LBA (MLBA) in the accumulator for the adding output of the PE. An MLBA approach is a significantly reduced area and increases speed by applying a looping transform function. Here, the proposed method is called a VM-MLBA-FIR filter. In this research, the FIR filter was done in Field Programmable Gate Array (FPGA) Xilinx by using Verilog code on various Virtex devices.FindingsThe experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.Originality/valueThe experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.

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Section: Introductionmentioning

confidence: 99%

Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA

Kumar¹,

Rangaraju²

2021

IJIUS

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“…The existing DA-based reconfigurable FIR filter yet to optimize the complexity in terms of adder delays and memory complexity are directly effecting on area, power and speed (Park and Meher, 2014;Budati and Polipalli, 2019). To address the issues discussed in literature, the proposed reconfigurable DA-based FIR with less number of LUTs has three fold advantages related to hardware structure, and those advantages are as follows: 1 For better sampling frequency, the number of taps is adjusted, and sampling rate is dependent of technology, which is required to adjust as per the block length.…”

Section: Proposed Methodology For Power Optimization Of Finite Impulse Responsementioning

confidence: 99%

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

Murthy

Sridevi

2021

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Purpose In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters. Design/methodology/approach The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer. Findings Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively. Originality/value The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

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“…The boundary error which is mean distance between the boundary of the obtained results and ground truth images were more consistently less is compared to semi-automated human annotator. Zilly et al (2017), Budati and Polipalli (2019) method is an improved version of two-way multi scale convolutional neural network with boosting approach. The simulation experiment has been performed using Drishti-GS and RIM-ONE database for performance analysis.…”

Section: Related Workmentioning

confidence: 99%

Automatic detection of optic disc using distance regularized level-set segmentation for glaucoma screening system

Patil

Rao

2021

IJIUS

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PurposeThe abnormalities of glaucoma have high impact on deciding and representing the causes that effects severity of blindness in human beings. The simulation experimental results would help the ophthalmologist in diagnosing of glaucoma abnormality accurately. The significant effect of glaucoma has a huge impact on the quality of human life, and its growth rate in world population tremendously increases. Glaucoma is considered as second largest cause for the blindness in the world; hence identification of it marks the importance of its detection at the earliest.Design/methodology/approachThe prime objective of the work proposed is to build up a human intervention free image preparing framework for glaucoma screening. The disc calculation is assessed on retinal image dataset called retinal Image for glaucoma Analysis. The proposed method briefs a novel optic disc division calculation depending on applying a level-set strategy on a confined optic disc image. In the instance of low quality image, a twofold level set is designed, in which the principal level set is viewed as restriction for the optic disc. To keep the veins from meddling with the level-set procedure, an inpainting strategy has been applied. Also a significant commitment is to include the varieties in notion adopted by the ophthalmologists in distinguishing the disc localization and diagnosing the glaucoma. Most of the past investigations are prepared and tested depending on just a single feature, which can be thought to be one-sided for the ophthalmologist.FindingsIn continuation, the correctness has been determined depending on the quantity of image that matched with the investigation pattern adopted by the ophthalmologist. The 175 retinal images were utilized to test the results of proposed work with the manual markings of ophthalmologists. The error-free calculation in marking the optic disc region and centroid was 98.95% in comparison with the existing result of 87.34%.Originality/valueIn continuation, the correctness has been determined depending on the quantity of image that matched with the investigation pattern adopted by the ophthalmologist. The 175 retinal images were utilized to test the results of proposed work with the manual markings of ophthalmologists. The error-free calculation in marking the optic disc region and centroid was 98.95% in comparison with the existing result of 87.34%.

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Performance analysis of HFDI computing algorithm in intelligent networks

Cited by 13 publications

References 8 publications

Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA

Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

Automatic detection of optic disc using distance regularized level-set segmentation for glaucoma screening system

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