Performance analysis of junctionless gate all around tunnel field effect transistor

Moni, D. Jackuline; Sundari, T. Jaspar Vinitha

doi:10.1109/icdcsyst.2016.7570604

Cited by 5 publications

(2 citation statements)

References 8 publications

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“…Semiconductor foundries translate the technology-specific data into a collection of library files and provide programming scripts, which can be used with the commercial electronic design automation (EDA) tools [10]. Specifically, these libraries and scripts are collectively known as a process design 1 FreePDK15TFEThttps://github.com/SJTU-YONGFU-RESEARCH-GRP/FreePDK15-TFET BSIM4 TFET [17] Notre Dame TFET [18] MIT TFET [19] Junction-less SG-TFET [20] Junctionless GAA-TFET [21] Universal TFET [22] III-V TFET kit (PDK). As shown in Fig.…”

Section: A Components Of Pdksmentioning

confidence: 99%

“…Tunnel field-effect transistors (TFETs) are one of the next-generation candidates to compete with CMOS transistors at low voltage operation as it is able to achieve a subthreshold swing of less than 60 mV/decade [27]. Since the first introduction of TFET model [28], several research communities have provided open-source TFET models [16], [17], supporting different types of TFET physical structure, such as single-gate (SG) [19], [29], [30], double-gate (DG) [31]- [33], and gate-all-around [20], [34].…”

Section: Open-source Tfet's Modelsmentioning

confidence: 99%

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FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

Chen

Zhang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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With Moore's law reaching its limits, the use of new materials or new devices' structure has emerged as the next generation of CMOS devices. Among all, tunneling field-effect transistors (TFETs) have achieved a steep sub-threshold slope of less than 60mV/decade yet there is a lack of a complete process design kit (PDK) for large-scale circuit design. Hence, we present an open-source 15nm TFET PDK (15nmTFETPDK), which is based on FreePDK15 with additional support for open-source TFET models and its associated Cadence Virtuoso pcell in OA format and Mentor Calibre physical verification files. Our users can design their circuit in the Cadence Virtuoso platform and verify the consistency of the drawn layout and the circuit through the Calibre Platform. We hope that this open-source PDK allows them to further advance their research with new emerging devices.

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Section: A Components Of Pdksmentioning

confidence: 99%

Section: Open-source Tfet's Modelsmentioning

confidence: 99%

FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

Chen

Zhang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Study and Analysis of Enclosed Gate FET’s

Vandana

Kumar

Shilla

et al. 2021

IOP Conf. Ser.: Mater. Sci. Eng.

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The characteristic and parametric dimensioning of Enclosed Layout (ELT) MOSFET with various geometric sizes and shapes has been taken into consideration for the study of irradiations and leakage at room temperature, which has been confirmed on several technological platforms. Using the most advanced technologies, parametric changes with minimum W/L ratios, layout area and input capacitance to reduce leakage current can improve the performance. The technique of hardening of the MOSFETs in contrary to total-dose radiation effects in space environment built in enclosure to the enclosed transistor for the elimination of edges, responsible of conventional NMOS transistors leakage path creation. High yielding, high level of integration, radiation immune, high speed, low costing and high volume production are the profit advantages of the enclosed layout.

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