Performance Analysis of the Impact of Design Parameters to Network-on-Chip (NoC) Architecture

Phing, Ng Yen; Warip, Mohd Nazri Mohd; Ehkan, Phaklen; Zulkefli, F. W.; Ahmad, R. Badlishah

doi:10.1007/978-3-319-59427-9_26

Cited by 3 publications

(3 citation statements)

References 4 publications

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“…VC behaves similar to having multiple wormhole channels present in parallel. However, adding extra VC to each link does not add bandwidth to the physical channel [14]. It just enables better sharing of the physical channel by different flows.…”

Section: Resultsmentioning

confidence: 99%

A efficacy of different buffer size on latency of network on chip (NoC)

et al. 2019

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Moore's prediction has been used to set targets for research and development in semiconductor industry for years now. A burgeoning number of processing cores on a chip demand competent and scalable communication architecture such as network-on-chip (NoC). NoC technology applies networking theory and methods to on-chip communication and brings noteworthy improvements over conventional bus and crossbar interconnections. Calculated performances such as latency, throughput, and bandwidth are characterized at design time to assured the performance of NoC. However, if communication pattern or parameters set like buffer size need to be altered, there might result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication while routers with small buffers reduce power consumption but result in high latency. This paper intention is to validate that size of buffer exert influence to NoC performance in several different network topologies. It is concluded that the way in which routers are interrelated or arranged affect NoC’s performance (latency) where different buffer sizes were adapted. That is why buffering requirements for different routers may vary based on their location in the network and the tasks assigned to them.

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Section: Resultsmentioning

confidence: 99%

A efficacy of different buffer size on latency of network on chip (NoC)

et al. 2019

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“…The performance such as low power consumption, low area, low latency, and high throughput are the main desirable characteristic for NoC architecture. However, the performance is drop as the number of cores is increasing [2]. This is because the number of cores is proportional to the average latency and total power consumption.…”

Section: Introductionmentioning

confidence: 99%

Reducing Total Power Consumption and Total Area Techniques for Network-on-Chip Through Disable Cores and Routers Based on Clustering Method

Phing¹,

Warip²,

Ehkan³

et al. 2018

IJEECS

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<span lang="EN-US">Network-on-Chip (NoC) is a promising solution to overcome the communication problem of System-on-Chip (SoC) architecture. The execution of topology, routing algorithm and switching technique is significant because it powerfully affects the overall performance of NoC. In the Network-on-Chip, the total power consumption increasing due to the large scale of network. In order to solve it, a clustering method and disable cores and routers based on clustering method is apply onto mesh based NoC architecture. In the proposed approach, the optimization of total area and total power consumption are the major concern. Experiment results show that the proposed method outperformas the existing work. The clustering-mesh based method reduced the total area by 22% to 40 % and total power consumption by 22% to 56% compare to mesh topology. In addition, the proposed method by disable cores and routers based on clustering-mesh based method has decrease the total area by 45% to 87% and total power consumption by 33% to 75% compare to mesh topology.</span>

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“…Many research works in the recent past, have attempted similar evaluation comparisons, none of them however has considered such a combined impact of all these aforementioned critical parameters together, in qualifying QoS in 2D NoC systems. Specifically in[10], a similar evaluation has been attempted but without considering a wide variety of traffic profiles, or buffering capability, in[11] the evaluation is restricted and focused mainly in selection strategy, while in[12] is focused in varying only network size. In[13], the evaluation is strictly based on uniform versus Hotspot traffic for two specific NoC topologies, while in[14], the evaluation is restricted in varying PIR.…”

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confidence: 99%

An Evaluation of Routing Algorithms in Traffic Engineering and Quality of Service Provision of Network on Chips

Lallas¹

2021

ENG

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Nowadays the number of cores that are integrated into NoC (Network on Chip) systems is steadily increasing, and real application traffic, running in such multi-core environments requires more and more bandwidth. In that sense, NoC architectures should be properly designed so as to provide efficient traffic engineering, as well as QoS support. Routing algorithm choice in conjunction with other parameters, such as network size and topology, traffic features (time and spatial distribution), as well as packet injection rate, packet size, and buffering capability, are all equivalently critical for designing a robust NoC architecture, on the grounds of traffic engineering and QoS provision. In this paper, a thorough numerical investigation is achieved by taking into consideration the criticality of selecting the proper routing algorithm, in conjunction with all the other aforementioned parameters. This is done via implementation of four routing evaluation traffic scenarios varying each parameter either individually, or as a set, thus exhausting all possible combinations, and making compact decisions on proper routing algorithm selection in NoC architectures. It has been shown that the simplicity of a deterministic routing algorithm such as XY, seems to be a reasonable choice, not only for random traffic patterns but also for non-uniform distributed traffic patterns, in terms of delay and throughput for 2D mesh NoC systems.

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Performance Analysis of the Impact of Design Parameters to Network-on-Chip (NoC) Architecture

Cited by 3 publications

References 4 publications

A efficacy of different buffer size on latency of network on chip (NoC)

A efficacy of different buffer size on latency of network on chip (NoC)

Reducing Total Power Consumption and Total Area Techniques for Network-on-Chip Through Disable Cores and Routers Based on Clustering Method

An Evaluation of Routing Algorithms in Traffic Engineering and Quality of Service Provision of Network on Chips

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