Performance analysis of various scheduling algorithms using FPGA platforms

Nazir, Liyaqat; Mir, Roohie Naaz

doi:10.1109/vlsi-sata.2015.7050477

Cited by 1 publication

(1 citation statement)

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“…In terms of FPGA implementation, none of the researchers have implemented the EXP-BET scheduling algorithm using the hardware platform. In 2015, the authors of paper [13] have focused on the implementation of various algorithms for an arbiter with low port density (8-bit) using FPGA platform. Round robin arbiter which led to strong fairness is selected and it works on the principle that a request that was just served should have the lowest priority on the next round of arbitration.…”

Section: Introductionmentioning

confidence: 99%

Hardware simulation for exponential blind equal throughput algorithm using system generator

Yusuf¹,

Ali²,

Ya’acob³

2019

IJECE

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Scheduling mechanism is the process of allocating radio resources to User Equipment (UE) that transmits different flows at the same time. It is performed by the scheduling algorithm implemented in the Long Term Evolution base station, Evolved Node B. Normally, most of the proposed algorithms are not focusing on handling the real-time and non-real-time traffics simultaneously. Thus, UE with bad channel quality may starve due to no resources allocated for quite a long time. To solve the problems, Exponential Blind Equal Throughput (EXP-BET) algorithm is proposed. User with the highest priority metrics is allocated the resources firstly which is calculated using the EXP-BET metric equation. This study investigates the implementation of the EXP-BET scheduling algorithm on the FPGA platform. The metric equation of the EXP-BET is modelled and simulated using System Generator. This design has utilized only 10% of available resources on FPGA. Fixed numbers are used for all the input to the scheduler. The system verification is performed by simulating the hardware co-simulation for the metric value of the EXP-BET metric algorithm. The output from the hardware co-simulation showed that the metric values of EXP-BET produce similar results to the Simulink environment. Thus, the algorithm is ready for prototyping and Virtex-6 FPGA is chosen as the platform.

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Section: Introductionmentioning

confidence: 99%