Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Hasegawa, Yohei; Amano, Hideharu; Abe, Sachiko; Kurotaki, S.; Vu, Manh

doi:10.1109/ipdps.2006.1639431

Cited by 8 publications

(6 citation statements)

References 9 publications

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“…Since the practical use of them has just started, the architectural trade-off has not been well analyzed qualitatively. However, some practical analysis results has been reported recently [7], [18], and in the near future, the optimal structure will be selected automatically when the target application and SoC are fixed.…”

Section: Resultsmentioning

confidence: 99%

A Survey on Dynamically Reconfigurable Processors

Amano¹

2006

IEICE Transactions on Communications

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Section: Resultsmentioning

confidence: 99%

A Survey on Dynamically Reconfigurable Processors

Amano¹

2006

IEICE Transactions on Communications

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“…According to Hasegawa [1], each implementation has an optimum context size (the number of tiles) where the performance becomes optimum. Other context sizes no matter whether they are smaller or larger than the optimum one result in performance degradation.…”

Section: Drp Architecturementioning

confidence: 99%

A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors

Tuan

Amano

2008

IEICE Transactions on Information and Systems

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SUMMARY The multi-process execution in dynamically reconfigurable processors is a technique to enhance throughput by trying to exploit more inherent parallelism of applications. Basically, a total process for an application is divided into small processes, assigned into limited areas of a reconfigurable array, and concurrently executed in a pipelined manner. In order to improve the efficiency of the multi-process execution, a systematic method for mapping processes onto a reconfigurable array consisting of multiple hardware execution units is essential. This paper proposes and investigates a systematic method for mapping an application modeled as a Kahn Process Network onto a dynamically reconfigurable processing array. In order to execute streaming applications in a pipelined manner, the size of Tiles, which is a unit area of dynamically reconfigurable array, and the grouping of processes are adjusted. Using real applications such as DCT, JPEG encoder and Turbo encoder, the impact of different versions mapped onto the NEC Dynamically Reconfigurable Processor on performance is evaluated. Evaluation results show that our proposed mapping algorithm achieves the best performance in terms of the throughput and the execution time.

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“…PE functionality, word bit width, the number of hardware contexts, the total amount of wiring resource, and the size of PE array itself are the examples. Our performance evaluation results revealed that the optimal PE array size considering the area and power consumption is different by each application [5]. Thus, there is no all-around architecture in DRPAs, and the structures should be configurable or customizable for their main target applications.…”

Section: Introductionmentioning

confidence: 99%

A study on interconnection networks of the Dynamically Reconfigurable Processor Array MuCCRA

Kato

Sano

Yoshihiro

et al. 2009

2009 International Conference on Field-Programmable Technology

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A Dynamically Reconfigurable Processor Array (DRPA) is consisting of a number of PEs, and its interconnection of PE array gives a large effect on the total area, energy and performance. However, there is no study of DRPAs focused on their PE network. In this paper, we designed four types of DRPAs based on MuCCRA, developed in MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project. They have different topologies, which are direct interconnection, island-style interconnection and two kinds of hybrid interconnection. They are evaluated using three different PE array sizes. As a result, a MuCCRA with hybrid network, which has the highest degree of connectivity, is able to execute DCT faster than the other MuCCRAs, but requires more area by 20% than MuCCRA with direct network. On energy consumption, MuCCRA with direct links consumes 7 times more energy at maximum than islandstyle-interconnected MuCCRAs.

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Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Abstract: Dynamically Reconfigurable Processor (DRP)

Cited by 8 publications

References 9 publications

A Survey on Dynamically Reconfigurable Processors

A Survey on Dynamically Reconfigurable Processors

A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors

A study on interconnection networks of the Dynamically Reconfigurable Processor Array MuCCRA

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