Performance and power of cache-based reconfigurable computing

Realising memory intensive applications such as image and video processing on FPGA requires creation of complex, multi-level memory hierarchies to achieve real-time performance; however commerical High Level Synthesis tools are unable to automatically derive such structures and hence are unable to meet the demanding bandwidth and capacity constraints of these applications. Current approaches to solving this problem can only derive either single-level memory structures or very deep, highly inefficient hierarchies, leading in either case to one or more of high implementation cost and low performance. This paper presents an enhancement to an existing MC-HLS synthesis approach which solves this problem; it exploits and eliminates data duplication at multiple levels levels of the generated hierarchy, leading to a reduction in the number of levels and ultimately higher performance, lower cost implementations. When applied to synthesis of C-based Motion Estimation, Matrix Multiplication and Sobel Edge Detection applications, this enables reductions in Block RAM and Look Up Table (LUT) cost of up to 25%, whilst simultaneously increasing throughput.

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Performance and power of cache-based reconfigurable computing

Cited by 18 publications

References 13 publications

A high level implementation and performance evaluation of level-I asynchronous cache on FPGA

A high level implementation and performance evaluation of level-I asynchronous cache on FPGA

A Parallel for Loop Memory Template for a High Level Synthesis Compiler

Memory-centric VDF graph transformations for practical FPGA implementation

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