Performance and Trends in Millimetre-Wave CMOS Oscillators for Emerging Wireless Applications

Voicu, Marius; Pepe, Domenico; Zito, Domenico

doi:10.1155/2013/312618

Cited by 17 publications

(18 citation statements)

References 16 publications

(36 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The simulations are repeated for three values of L 3 in order to show the weak dependence of the oscillation frequency f 0 on L 3 . This means that L 3 can be sized to satisfy other design requirements, with limited effects on the oscillation frequency.…”

Section: Oscillation Frequencymentioning

confidence: 99%

“…Here, our aim is to explore the dependence of PN on L 3 and derive under which condition the PN in the output spectrum of the Hartley oscillator circuit topology of Figure 2(a) could be minimized. The theoretical results will be compared with respect to the simulation results obtained by means of SpectreRF.…”

Section: Optimum Inductance For Minimum Phase Noisementioning

confidence: 99%

“…Despite significant advances in recent years, achieving low PN is still a severe challenge [1][2][3][4], especially at high frequency. Despite significant advances in recent years, achieving low PN is still a severe challenge [1][2][3][4], especially at high frequency.…”

Section: Introductionmentioning

confidence: 99%

“…Phase noise (PN) in voltage-controlled oscillators (VCO) is sensibly responsible for performance degradation in radiofrequency (RF) transceivers. Despite significant advances in recent years, achieving low PN is still a severe challenge [1][2][3][4], especially at high frequency.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Analyses and techniques for phase noise reduction in CMOS Hartley oscillator topology

Chlis

Pepe

Zito

2017

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

This paper reports the analyses of the inductive degeneration, noise filter, and optimum current density techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. The design of the circuit topology is carried out in 28 nm bulk CMOS technology in a range of common conditions adopted also for a previous study on the Colpitts topology, so complementing the previous study on Colpitts topology and allowing a direct comparison between the Hartley and Colpitts topologies. The theoretical analyses of the three techniques are carried out and verified by means of circuit simulations. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. Moreover, the results obtained for the optimum bias current density technique applied to a Hartley oscillator circuit topology incorporating either inductive degeneration or noise filter provide the demonstration of the existence of an optimum bias current density for minimum phase noise. Moreover, we will go beyond this important result, by investigating for the first time the relationship with the optimum current density for transistor minimum noise figure and other general results reported in the literature. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 16 dB at a 1 MHz frequency offset for an oscillation frequency of 10 GHz, with respect to the traditional Hartley topology. Lastly, we report a comparison under common conditions between Colpitts and Hartley topologies implementing the aforementioned techniques, which could, from a designer perspective, be useful to acquiring a few key insights about the circuit design opportunities and focus the design efforts toward specific directions for performance optimizations. that the Hartley topology with inductive degeneration can lead potentially to a PN reduction up to 10 dB.Lastly, the results presented in [5] show that the 1/f 3 region of the PN extends above a 1 MHz frequency offset for the Hartley oscillator circuit topology under study. This can be attributed to the adoption of nanoscale CMOS technologies characterized by flicker noise corners of several tens or hundreds of MHz, which lead to flicker noise upconversion being responsible for most of the PN even at large offsets from the carrier frequency. Thereby, the optimum inductance value for the total PN shown in Figure 5 is very close to that given by (7)-(9), because at a 1 MHz offset, thermal noise has a negligible effect on PN. NOISE FILTERIn this section, we will derive the analytical expression for the oscillation frequency (f 0 ) of a Hartley oscillator circuit topology in which we introduced a noise band-stop filter (L 4 , C 4 ) to the source node of M 1 as shown in Figure 7(a). Because of its noise filtering action, it is referred therein [8] as noise filter. Moreover, we will observe that there is an optimum inductance value (L 4 ) for which the Figure 7. (a) Hartley oscillator circuit topology...

show abstract

Section: Oscillation Frequencymentioning

confidence: 99%

Section: Optimum Inductance For Minimum Phase Noisementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analyses and techniques for phase noise reduction in CMOS Hartley oscillator topology

Chlis

Pepe

Zito

2017

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

show abstract

“…Therefore, for the first time in the telecommunication history, bands above 90 GHz are studied for future communications [1]. In particular, mmWave systems are critically impacted by phase noise (PN) due to the poor performance of high frequency oscillators [2]. This has motivated extensive work on PN estimation and compensation [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Adaptive PSK Modulation Scheme in the Presence of Phase Noise

Bicaïs

Doré

González-Jiménez

2018

2018 IEEE 19th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC)

View full text Add to dashboard Cite

Abstract-Phase noise is one of the major impairments affecting severely performance of millimeter-wave systems. This paper addresses the problem of link adaption for coherent and non-coherent phase modulated signals subject to Gaussian and Wiener phase noise. We first derive closed-form approximations of the bit error rate. Then, in contrast to usual link adaptation techniques, we propose a simple scheme exploiting estimations of not only the signal-to-noise ratio but also of the phase noise variance, which is essential to achieve reliable communications.

show abstract

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

Chlis

Pepe²,

Zito

2015

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

SUMMARYThis paper reports the analyses of three techniques for phase noise reduction in the complementary metaloxide semiconductor (CMOS) Colpitts oscillator circuit topology. Namely, the three techniques are inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28-nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB at a 1-MHz frequency offset for an oscillation frequency of 10 GHz.

show abstract

Performance and Trends in Millimetre-Wave CMOS Oscillators for Emerging Wireless Applications

Cited by 17 publications

References 16 publications

Analyses and techniques for phase noise reduction in CMOS Hartley oscillator topology

Analyses and techniques for phase noise reduction in CMOS Hartley oscillator topology

Adaptive PSK Modulation Scheme in the Presence of Phase Noise

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

Contact Info

Product

Resources

About