Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits

Analog Integrated Circuit Routing Techniques: An Extensive Review

“…transformers/inductors, that are built on the thick top metals do not change much between nodes, even with the scaling on the deep metals of the technology. Even inductor-less designs, like the one reported in [11], can perform with the same or better noise in 16 FinFET as in 40, 65, or 90nm, this can be achieved with proper design and by being mindful during the layout. Therefore, since the earliest approaches, analog routing techniques have also attempted to introduce performance-related criteria either by separating noise and sensitive nets on the layout or minimizing coupling parasitics among different wires of the different nets.…”