Performance Comparison of Adder Topologies with Parallel Processing Adder Circuit

Abstract

In today’s modern era IC architecture design adders are become obligatory block. The growth in digitalization scenario to produce compact design products parameters like power, delay and area should be minimized. In most of the complex design of digital circuits, adder is an elementary factor. If the performance of digital adders is enriched, it would lead to quickening the binary operations in involved in the complex circuits. The constraints in the operation delay of an adder are due to carry propagation in the circuit. The adder topologies involved in this work includes Carry Save Adder, Carry Select Adder, Ripple Carry Adder and Kogge Stone Adder