Performance enhancement in a novel amalgamation of arsenide/antimonide tunneling interface with charge plasma junctionless-TFET

Sharma, Shikha; Chaujar, Rishu

doi:10.1016/j.aeue.2021.153669

Cited by 19 publications

(10 citation statements)

References 29 publications

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“…This issue can be resolved by incorporating compound semiconducting hetero-material bandgap engineering at the S/C interface of JLTFET. The tunable bandgap leads to tunnel barrier lowering at the S/C interface and hence the tunneling probability of the carriers increases leading to higher ON current [14]. The channel length, oxide thickness, and body thickness are taken as 20 nm, 2 nm, and 3 nm, respectively.…”

Section: Device Architecture and Simulationmentioning

confidence: 99%

“…Moreover, the fabrication of physically doped devices faces significant challenges such as dopant diffusion, threshold voltage variability, high temperature processing, abrupt junction formation, and scaling limitations [11,12]. As semiconductor technology continues to advance toward smaller feature sizes and greater performance demands, junctionless TFETs have been designed using the charge plasma concept to hold promise in addressing some of the issues associated and to resolve the fabrication complexity and junction constraint [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

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Interfacial charge associated reliability improvement in arsenide/antimonide tunneling interfaced-junctionless TFET

Sharma,

Madan,

Chaujar

2024

Phys. Scr.

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This article focuses on the investigation of reliability improvement in the arsenide/antimonide tunable bandgap tunneling interfaced junctionless TFET (HD-HJLTFET) by introducing positive (donor) and negative (acceptor) localized interfacial trap charges (ITCs) at the semiconductor/oxide (S/O) and semiconductor/semiconductor (S/S) interface. The compound semiconducting materials, InAs (lower bandgap) and AlGaSb (higher bandgap) have been incorporated in the source and channel regions in the proposed device (HJLTFET). Further, to improve the device reliability against ITCs, a hetero dielectric engineered gated device has also been designed and analysed (HD-HJLTFET). In HD-HJLTFET, a high-k dielectric near source to channel (S/C) interface and low-k dielectric region towards drain to channel (D/C) interface has been used. It has been obtained that HD engineering enhances the microwave and harmonic distortion performance of HD-HJLTFET. It has been evaluated that HD-HJLTFET/ HJLTFET delivers ON current of 38.3µA/14µA, transconductance 108µS/23.2µS, cut-off frequency 805.8GHz/406.7GHz and gain of 223.5/197.4. Further results show that HD delivers gm2 (~28% ↓), gm3 (~ 9 times), second-order and third-order harmonic distortion (~42% ↓ and ~90% ↓), and total harmonic distortion (~26% ↓) as compared to HJLTFET. The linearity parameters of HD-HJLTFET (VIP2, VIP3, IIP3, 1dB compression point, and IMD3) also showed marked improvement with negligible variation against different ITC polarity than its counter device, making it more reliable for low power microwave and distortion-free wireless communication systems.

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Section: Device Architecture and Simulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Interfacial charge associated reliability improvement in arsenide/antimonide tunneling interfaced-junctionless TFET

Sharma,

Madan,

Chaujar

2024

Phys. Scr.

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“…The prime reason for low I ON is the large bandgap of Si (~1.1 eV), 10,11 which brings on an inadequate quantum band‐to‐band tunneling through the barrier. This hitch can be solved by employing low bandgap semiconducting materials or III–V compound semiconducting materials like

italicInAs, italicGaAs, italicInP, italicSiGe

12–16 ; however, it becomes challenging to use III–V compound semiconducting materials for making selective oxide formation due to the problem of lattice incongruity.…”

Section: Introductionmentioning

confidence: 99%

“…A JLTFET is a uniformly doped junctionless TFET, whose fundamental mechanism of carrier polarity induction is charge plasma. The basic idea of charge plasma concept is to convert a highly doped

n^{+} - n^{+} - n^{+}

substrate into the conventional

p^{+} - i - n^{+}

substrate by using two different work function gates as the polar gate (PG) and a control gate (CG) 11,16 . By using charge plasma concept, the involuted fabrication processes, arbitrary doping fluctuations, and scalability issues can be reduced adequately.…”

Section: Introductionmentioning

confidence: 99%

Impact of tunnel gate process variations on analog/radio frequency (microwave) and small signal parameters of hetero‐material tunneling interfaced charge plasma junctionless tunnel field effect transistor

Sharma

Chaujar

2022

Circuit Theory & Apps

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This paper proposes a dual metal gate, hetero-material tunneling interfaced junctionless tunnel field effect transistor (TFET), (DMG-HJLTFET), utilizing III-V compound semiconducting materials, InAs (low band-gap source material)/GaAs (higher band-gap channel and drain material) by applying the band-gap and dual material gate engineering. The 2-D TCAD simulations have been executed to explore the impact of tunnel gate process variations-work function and length on DC and analog figure of merits (FOMs) of DMG-HJLTFET. The extracted result parameters have also been compared to SMG (single metal gate)-HJLTFET and conventional Si-JLTFET. The DMG-HJLTFET attains improved ON current in the range of 88.5 Â 10 À6 A/μm and OFF current remains as low as 2.89 Â 10 À16 A/μm. It exhibits a high current switching ratio of 3.1 Â 10 11 as compared to SMG-HJLTFET (I ON = 24 Â 10 À6 A/μm and I ON /I OFF = 1.4 Â 10 11 ) and Si-JLTFET (I ON = 7 Â 10 À6 A/μm and I ON /I OFF = 1.8 Â 10 6 ). Further, the radio frequency/microwave (RF) parameters such as power gains (h 12 , UPG, and Gma), f max , and GBP have been compared for all three aforementioned devices. Moreover, the small signal admittance (Y) parameters have been examined to explore the possible scope of DMG-HJLTFET for future internet of everything communications and fast switching applications.

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“…TFETs possess unique characteristics that make them ideal for various applications, such as low-power, analog/RF, and optosensing devices. [10][11][12][13][14] TFET, on the other side, has certain drawbacks, including a large ambipolar [15][16][17][18][19][20] conduction, minimum ONstate current, and poor performance at high frequency. 8 The Zshaped Horizontal Pocket (ZHP) 13,14 is a new architecture that has been considered as a solution to address these problems.…”

mentioning

confidence: 99%

Electrical Noise Analysis of Z Shape Horizontal Pocket and Hetero Stack TFETs under Trap Distribution

Tiwari¹,

Saha²

2022

ECS J. Solid State Sci. Technol.

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A comprehensive investigation on noise analysis for two different low-power devices, namely Z-shaped Horizontal Pocket and hetero stack tunnel field-effect transistors (TFETs), is presented within low- to high-frequency range. The simulation is performed for these structures in the presence of uniform and Gaussian trap distributions at the interface of Silicon and oxide materials for three different noise namely flicker noise, generation recombination (GR) noise, and diffusion noise with the help of the Sentaurus TCAD simulator. The result reveals that flicker and GR noise are dominates at low frequency, while, the diffusion noise reports significant influence at the high-frequency range. Finally, a comparative analysis has been done in terms of noise current spectral density (Sid) of the considered structures with the existing literature.

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Performance enhancement in a novel amalgamation of arsenide/antimonide tunneling interface with charge plasma junctionless-TFET

Cited by 19 publications

References 29 publications

Interfacial charge associated reliability improvement in arsenide/antimonide tunneling interfaced-junctionless TFET

Interfacial charge associated reliability improvement in arsenide/antimonide tunneling interfaced-junctionless TFET

Impact of tunnel gate process variations on analog/radio frequency (microwave) and small signal parameters of hetero‐material tunneling interfaced charge plasma junctionless tunnel field effect transistor

Electrical Noise Analysis of Z Shape Horizontal Pocket and Hetero Stack TFETs under Trap Distribution

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