Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

Pande, Partha Pratim; Grecu, C.; Jones, Mark T.; Ivanov, A.; Saleh, R.

doi:10.1109/tc.2005.134

Cited by 702 publications

(311 citation statements)

References 26 publications

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“…The NoC switch model is based on the pipelined model [13]. By default, a three-stage pipeline corresponding to an input/output buffering scheme is employed, shown in Fig.…”

Section: B Router Modelmentioning

confidence: 99%

A flexible network-on-chip simulator for early design space exploration

Grecu¹,

Ivanov²,

Saleh³

et al. 2008

2008 1st Microsystems and Nanoelectronics Research Conference

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Abstract-The communication requirements of large multi-core systems are convened by on-chip communication fabrics generally referred to as networks-on-chip (NoC). We have designed a simulation environment that allows early exploration of the performance and cost parameters of network-on-chip communication architectures, which is able to handle arbitrary topologies and routing schemes. The simulator implements a flit-level message-passing mechanism and supports application data specified as input trace files or generated at run-time by synthetic traffic generators.

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“…The NoC switch model is based on the pipelined model [13]. By default, a three-stage pipeline corresponding to an input/output buffering scheme is employed, shown in Fig.…”

Section: B Router Modelmentioning

confidence: 99%

A flexible network-on-chip simulator for early design space exploration

Grecu¹,

Ivanov²,

Saleh³

et al. 2008

2008 1st Microsystems and Nanoelectronics Research Conference

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show abstract

“…The structured nature and simple functionality of the NoC interconnect infrastructures render them particularly suitable for the implementation of these features (similar to the case of memory blocks, where yield enhancement and defect tolerant techniques have become common place [4]). The impact of these techniques on the overall yield of a NoC-based chip can be quite significant, given that the data communication infrastructure alone can consume around 10-15% of the total chip area [5]. More importantly than the area argument, the NoC inter-switch links are likely to be placed on the upper metal layers, and hence, the layout scenario is very similar to the situation shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

NoC Interconnect Yield Improvement Using Crosspoint Redundancy

Grecu

Ivanov

Saleh

et al. 2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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“…To be able to adapt with faults without serious degradation of the service, networks and routing protocols have to be set up so that they are fault-tolerant. Several recent studies address faulttolerance in a diverse range of systems and applications [1][2][3][4][5][6][7][8][9][10][11][12]. Almost all of the performance evaluation studies for functionality of these systems, however, have made use solely of simulation experiments.…”

Section: Introductionmentioning

confidence: 99%

On the Probability of Facing Fault Patterns: A Performance and Comparison Measure of Network Fault-Tolerance

Safaei

Khonsari

Moraveji

2008

Computational Science – ICCS 2008

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Abstract. An important issue in the design and deployment of interconnection networks is the issue of network fault-tolerance for various types of failures. In designing parallel processing using torus as the underlying interconnection topology as well as in designing real applications on such processors, the estimates of the network reliability and fault-tolerance are important in choosing the routing algorithms and predicting their performance in the presence of faulty nodes. Under node-failure model, the faulty nodes may coalesce into fault patterns, which classified into two major categories, i.e., convex (|-shaped, -shaped) and concave (L-shaped, T-shaped, +-shaped, H-shaped, U-shaped) regions. In this correspondence, we propose the first solution for computing the probability of message facing the fault patterns in tori both for convex and concave regions that is verified using simulation experiments. Our approach works for any number of faults as long as the network remains connected. We use these models to measure the network faulttolerance that can be achieved by adaptive routings, and to assess the impact of various fault patterns on the performance of such networks.

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Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

Cited by 702 publications

References 26 publications

A flexible network-on-chip simulator for early design space exploration

A flexible network-on-chip simulator for early design space exploration

NoC Interconnect Yield Improvement Using Crosspoint Redundancy

On the Probability of Facing Fault Patterns: A Performance and Comparison Measure of Network Fault-Tolerance

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