Performance evaluation of a novel Dimension Order Routing algorithm for Mesh-of-tree based Network-on-Chip architecture

Abstract

This paper present a new dimension-oriented routing algorithm for Mesh-of-tree (MoT) based Network-on-Chip (NoC) architecture. The addressing scheme is considerably simplified that enables us to reduce the minimum flit-size to 16-bits, compared to 32-bits in the previously reported works. The same level of throughput and average latency could be achieved with a 43.86% reduction in area and 43% reduction in energy. Bandwidth can be increased via increasing flit size. The design of the new router enables us to select routers of various complexities with performance trade-offs required for real-life application.