Performance evaluation of Distributed Arithmetic based MAC Structures for DSP Applications

Bharathi, M.; Shirur, Yasha Jyothi M; Lahari, P.L.

doi:10.1109/icsss49621.2020.9202003

Cited by 10 publications

(1 citation statement)

References 2 publications

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“…In the literature, subexpression elimination has been used [19], [20] for applications with multiple constant multiplication arithmetic operations such as FIR filter implementations. Furthermore, distributed arithmetic [21] has been also proposed for optimized DSP implementations where constants are involved [22], [23]. Beyond DSP applications, Navarro et al [24] proposes a way to accelerate the arithmetic reduction for the case of summations in a GPU core, by exploiting distributed arithmetic.…”

Section: Introductionmentioning

confidence: 99%

Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference

Kouretas

Paliouras

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper a simplified hardware implementation of a dot product arithmetic operation with constant coefficients is presented. The proposed methodology exploits a combination of distributed arithmetic and common subexpression sharing techniques. An algorithm is introduced for identifying the common sub partial sums systematically. Subsequently, a hardware architecture is proposed and the obtained circuits are synthesized in a 90-nm 1.0 V CMOS standard-cell library using Synopsys Design Compiler. Comparisons reveal significant reduction of 52% and 23% in area and power respectively for 1.5 ns delay over a regular dot product constant multiplier.

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