Performance evaluation of five‐level packed U‐cell inverter and its fault‐tolerant variants

Abstract

SummaryIn the power electronics industry, reliability is of utmost importance to manufacturers. Power semiconductor devices are extensively utilized in multilevel inverters (MLIs), which results in increased failure probability. MLI structures have a significant impact on the system's overall reliability. MLIs with a high degree of reliability reduce system maintenance costs and improve efficiency and the life of the entire system. This paper presents a comprehensive evaluation of five‐level packed U‐cell (PUC5) inverter, modified five‐level PUC (MPUC5) inverter, and their fault‐tolerant (FT) variants with respect to reliability, degree of fault tolerance, power loss and efficiency, and cost. A more accurate reliability evaluation method is used in this work in which failure rates of each component of inverter topologies under healthy and post‐fault conditions are calculated. Hence, this method provides more accurate reliability function of an MLI topology as compared to other methods in which failure rates are assumed to be same for all switches. Typhoon HIL‐402 emulator is used to demonstrate the FT capabilities of topologies in hardware‐in‐the‐loop (HIL) environments.