Performance evaluation of turbo encoder implementation on a heterogeneous FPGA-CPU platform using SDSoC

Adawy, M. El; Kamaleldin, Ahmed; Mostafa, Hassan; Said, S. M.

doi:10.1109/accs-peit.2017.8303053

Cited by 1 publication

(2 citation statements)

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“…The BCJR algorithm calculates forward probabilities, backward probabilities, and smoothed probabilities based on channel information. 14 The operation of turbo decoder is done as follows: (1) The MAP_decoder_1 accepts the systematic_bits and parity_bits then generates the extrinsic_bits1 (extrinsic bit is a soft estimate bits do not contain any information). (2) The extrinsic_bits1 bits are interleaved and generates extrinsic_interleaved_bits1; also, the systematic bits are interleaved and generates systematic_interleaved_bits.…”

Section: Channel Coding and Channel Decodingmentioning

confidence: 99%

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Automated performance‐based design technique for an efficient LTE PDSCH implementation using SDSoC tool

Eladawy

Mahmoud

Said

et al. 2019

Int J Communication

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System on a chip (SoC) creates massive design challenges for SoC-based designers. The design challenges start from functional, architectural verification complexity and finally meeting performance constraints. In addition, heterogeneity of components and tools introduces long design cycles. The Software-Defined System-on-Chip (SDSoC) developed by Xilinx is used to create custom SoC on a heterogeneous FPGA-CPU platform. The SDSoC tool provides fast, flexible, and short design cycle to develop heterogeneous FPGA-CPU platform. The objective of this paper is to introduce a new automated design technique to build a SoC on a heterogeneous FPGA-CPU platform that meets design requirements using SDSoC tool. In this paper, the typical SDSoC design flow is introduced. In addition, a new automated SDSoC design technique is developed to design SoC on a heterogeneous FPGA-CPU platform on the basis of performance metrics such as area, power, and latency. Design of physical downlink shared channel (PDSCH) in long-term evolution (LTE) is presented as a case study. This paper provides the implementation of the transmitter and the receiver of the PDSCH in LTE using SDSoC tool and selects a platform that meets performance metrics constraints.After refining all C/C++ functions, the SDSoC design flow is executed. 7 The SDSoC design flow is shown in Figure 2. First, all C/C++ functions are compiled, Next, the implementation of the C/C++ functions is partitioned into software implementation functions or hardware-accelerated functions depending on the designer selection.The Vivado tool (Xilinx Inc) and Software Development Kit (SDK) tool are the elements of hardware and software system design, respectively. The Vivado tool includes an HLS tool used for creating the hardware system components by transforming the C/C++ code to an RTL implementation. The SDK tool is a software design suite that includes driver support, C/C++ compiler library, and tools for debugging and profiling. Finally, for integration, the necessary communication blocks between hardware and software are generated automatically by the SDSoC tool, and SoC platform is created by SDSoC tool.The SDSoC tool generates the embedded FPGA SoC platform as shown in Figure 3. This platform allows executing parts of the C/C++ code on the ARM processor as software functions and the other parts of the C/C++ codes on the FPGA as hardware-accelerated functions. The embedded FPGA platform consists of three parts: First, the processing system includes dual-core ARM cortex-A9 processor hardcore processor. Second, interfacing logic includes ACP port interconnect and data movers. Third, hardware logic includes HLS generated block. | Proposed automated performance-based design techniqueThis section illustrates in detail the proposed automated performance-based design technique using SDSoC tool. The objective of this technique is to determine platforms that achieve performance metrics and to select the platform that achieves the best performance. Figure 4 shows the proposed automated performanc...

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Section: Channel Coding and Channel Decodingmentioning

confidence: 99%

“…The column permutation of the sub-block interleaver is given as follows: [0, 16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23,15,31]. The bit_collection block accepts input from three sub-block_interleaver and generates output depending on coding type.…”

Section: Rate Matchings and Rate De-matchingmentioning

confidence: 99%